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To: Timothy Liu who wrote (64489)	9/11/1998 2:57:00 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 186894

My experience with PCI is because it is a synchronous protocol, it is hard to achieve very high frequency. It maybe a last effort to squeeze some extra life into PCI. I am still curious how they achieve 133Mhz on the bus because I remember 66Mhz was a challenge a couple of years back. Micron's PII PC based on the Samurai chipset has 1 64bit 66Mhz PCI slot. I think the mention of those "enhancements to efficiency" may clue us in on how the 133 MHz speed might be achieved. I'll bet that the PCI-X protocol is actually a dual-mode protocol much like AGP. On the AGP bus, you have two types of transactions: AGP and PCI-semantic. Both types of transactions can occur concurrently, although there are a lot of protocol rules to make sure the PCI and AGP transactions don't interfere with each other. What I can't figure out is how they are going to implement backwards compatibility in terms of different clock frequencies. If you plug a 33 MHz PCI card into a 66 MHz PCI bus, the entire bus slows down to 33 MHz because of that one card. (The OS at this point would probably prompt the user to move that card to a 33 MHz slot.) If the same thing is true for PCI-X, then backwards compatibility with the original PCI 2.1 spec is meaningless. My guess is that PCI-X could still be a 66 MHz bus with a new double-pumped data transfer mode, like AGP once again. I'm still looking for that PCI-X draft. I'd appreciate it if someone could provide me with a link. Tenchusatsu