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To: Scumbria who wrote (65448)9/25/1998 3:52:00 PM
From: Tony Viola  Read Replies (2) | Respond to of 186894
 
Scumbria, Re: "It would be absurd to use an MP bus/memory
controller in a single processor system, because of the overhead involved in the
cache coherency protocols."

Fine, but who is going to take it to the next level, i.e., motherboard, node, server, clustered servers...Dell? Compaq? IBM? HP? I don't think so. For servers, reliability can take precedent even over speed. AMD has no experience in high rel. mission critical applications. In fact, their history of protracted yield problems very recently, to me, hints of poor reliability. One begets the other.

Tony



To: Scumbria who wrote (65448)9/25/1998 6:48:00 PM
From: Elmer  Read Replies (1) | Respond to of 186894
 
Re: "It would be absurd to use an MP bus/memory controller in a single processor system, because of the overhead involved in the cache coherency protocols."

Intel's been doing it for years with PPro & PII. Now low cost Celerons have the same full MP bus/memory controller as well.

EP


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