More on the MPEG-2 encoders and decoders at the JES...............
eet.com
Video encoders and decoders
unveiled at JES
By Anthony Cataldo
EE Times
(10/09/98, 2:48 p.m. EDT)
OSAKA, Japan — MPEG-2 decoder and
encoder devices may be chips looking for sockets
they can plug into, but there were plenty at the
Japan Electronics Show as vendors here and
abroad offered sneak peeks into what they will
integrate — and perhaps just as importantly what
they won't — in a raft of devices they are set to
trot out in early 1999.
On the encoder front, Sony and Matsushita will roll
out new devices that the companies claim integrate
all the most essential logic functions into one chip.
Their hope is to spur demand for video recording
and editing on a PC, an application that some
observers said is one of the few that PC users
might get excited about in the near term.
And despite a slow start for multimedia-rich
set-top boxes, there will soon be a rollout of
MPEG-2 decoder chips that will have more
wide-ranging support for international descrambling
schemes; have the ability to share data with
different peripheral devices such as smart cards;
and will swallow 2-D processing functionality,
thanks to the integration capabilities made possible
by the new 0.25-micron process technologies that
are just now going into high gear.
By the first quarter of 1999, Sony will try to spark
consumer interest in video capture on the PC by
spinning a 4.5-million-transistor MPEG-2 decoder
that includes motion estimation and a
programmable DSP-based controller. Sony will
use the device for a PCI add-in card that will be
bundled into a forthcoming Vaio desktop PC later
this year, and will begin to sell the device in the
open market by the first quarter of next year, said
Syuji Suzuki, an IC design engineer with Sony's
semiconductor division.
The most remarkable feature of the CXD192xQ
architecture is its wide-motion vector-search range,
which is 288 for the vertical pixel axis and 96 for
the horizontal axis (with an accuracy of 0.5 pixels).
"Usually when we pan video fast from left to right
or right to left, the picture is noisy and dirty. But
having such a wide range allows you to eliminate
this noise," Suzuki said.
The decoder also targets low power consumption.
The first chip, the CXD1922Q, will be produced
using a 0.35-micron process and will burn 1.2
watts. However, Sony plans to almost
simultaneously start ramping up 0.25-micron
versions that will consume 800 milliwatts, he said.
The device also features a Main Profile @ Main
Level (MP@ML) MPEG-2 decoder that can
process both NTSC (National Television
Standards Committee) and PAL formats at 30 and
25 frames per second, respectively, and a
homegrown DSP encoding controller that runs
independently of the host CPU and allows
designers to program functions like bit rate,
encoded image size and quantization matrix tables.
The maximum bit rate is 15 Mbits/second (I, B, P
frames) and 25 Mbits/s (I only).
The chip interfaces to a 16-bit external host CPU,
a CCIR-601 video input and up to 32 Mbits of
SDRAM. The host interface also outputs to an
8-bit video elementary stream. Scheduled to begin
sampling in early 1999, the device will be housed in
a 208-pin package.
Meanwhile, Matsushita Electronics Corp. will
sample by the end of this year its own MPEG-2
encoder device, packaged in a 208-pin plastic
QFP (quad flat pack), which will sport a motion
estimation engine and on-board 16-bit RISC
MPU.
The company demonstrated two possible uses for
the device. In one configuration, it could be used as
an appendage to a PC by connecting to an external
bus bridge, allowing it to execute DMA transfers
from PC main memory, latch on to the PCI bus to
transfer compressed video data and interface to an
external clock. In the second configuration, with
the inclusion of a piece of glue logic between the
encoder and a separate microcontroller, the chip
becomes a stand-alone encoder for DVD
recorders or MPEG-2 camcorders .
Matsushita designed the device as a low-power
module in order to give it the flexibility it needed.
Operating from either a 1.8-V or 3.3-V voltage
supply, the chip consumes 95 mW when encoding
MPEG-2 images and 36 mW for MPEG-1, giving
designers the ability to make trade-offs between
resolution and power consumption.
Video input data streams into the chip in an ITU-R
Rec. 656 (8-bit) format, and is compatible with
NTSC and PAL signals. The device outputs video
data in either PES or elementary-stream format.
The chip can also interface with up to 32 Mbits of
SDRAM memory.
Motion estimation is performed using a variable
search-area technique with a horizontal width of 63
pixels and a vertical depth of 47.5 pixels. The bit
rate is variable and can be set to a maximum of
15Mbits/s.
At the other end of the MPEG-2 processing
spectrum, NEC, Philips and Toshiba were showing
slides of future decoders aimed at set-top boxes.
The companies plan to use these devices for the
purposes of descrambling, decoding digital video
or in some cases graphics data and terrestrial and
cable data pipes. All of the devices incorporate a
microprocessor, demultiplexer and descrambler on
the same chip, and in two of the cases, also include
a 2-D graphics engine.
By next spring, NEC Corp. plans to send out
samples of its 0.25-micron PD61030 set-top box
chip. Packaged in a 304-pin plastic QFP, the
device integrates a VR4110 core that supports the
MIPS 1, 2 and 3 instruction set, an MPEG-2
transport stream demultiplexer, a digital video
broadcast (DVB) descrambler, MPEG-2 A/V
decoder, graphics engine, video encoder, a video
DAC and interfaces for several peripherals. The
chip also has memory interfaces to SDRAM and
non-volatile ROM and flash memory.
Video data comes into the chip via modem, an
ISDN interface or a satellite receiver. In the latter
case, the device interfaces with an external QPSK
(quadrature phase shift keying) mixed-signal
front-end chip, such as NEC's PD61511.
Among some of its most notable features is a CPU
capable of 100 Mips; a 12.5-Mbyte/second
parallel MPEG-2 transport stream; decode for
MPEG-2 MP@ML and MPEG-1 video with
audio layers 1 and 2; a graphics engine that
performs alpha blending, still plane, OSD plane
and BitBLT transfers; NTSC/PAL video output;
support for smart cards, I2C, IEEE 1284 and
UART; audio and video error concealment; and a
2.5-V voltage supply with a 3.3-V interface,
according to a preliminary data sheet.
Philips, meanwhile, made a preliminary
presentation of its STB6000 device, which absorbs
the transport-stream functions and MPEG-2
decoding functions that the company now offers as
separate devices. The company hopes to begin
sampling the chip by 2000, said Hisashige
Harashima, a product marketing representative of
Philips Japan Ltd. (Tokyo).
The chip will be capable of descrambling DVB
signals, Japan's Multi-2, and Europe's Icam. It
includes a DVB multiplexer, MPEG-2 decoder, an
encoder for NTSC/PAL and Secam, and a 32-bit
PR3940 MIPS-based CPU.
Harashima said Philips will target the device for
low-cost set-top box designs, although the
company is simultaneously positioning its
VLIW-based TriMedia processor for digital
satellite applications. "TriMedia is expensive.
Hardware is a bit cheaper solution for our
customers," he said.
Interestingly, Philips and NEC, which are among
the biggest cheerleaders for the IEEE 1394
interface for consumer applications, have no solid
plans to include the serial interface in their
forthcoming set-top box devices. Philips has a
tentative plan to include digital processing for 1394
with its STB6000 chip, but Harashima said those
plans may change depending on market conditions.
NEC showed an external 1394 interface as one
application example for PD61030, but the chip
itself includes no native support for the standard.
Toshiba, however, said it will include a 1394 link
as part of its TC81230F MPEG-2 decoder chip,
which is slated to roll out next June. The company
said it regards 1394 as a necessary function for the
evolution of the set-top box as envisioned by the
OpenCable specification, which dictates how
set-top boxes will process signals for HDTV. "We
think the set-top box will change into a home
terminal device," said Mieko Takahashi, a
representative of Toshiba's semiconductor system
marketing department (Tokyo).
Toshiba's chip includes a TX39 MIPS-based
CPU, descrambler, 2-D graphics controller,
SDRAM controller, MPEG-2 video decoder and
AC-3 audio decoder. Along with 1394, the chip
interfaces to a modem, smart card and PCMCIA
peripheral devices.
Takahashi said the chip can be used for a DVD
player, a set-top box or a combination of the two if
it includes external copy protection. It can also be
used in an Internet box using an external CPU, she
said. |
