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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (39174)	10/13/1998 2:32:00 PM
From: Joe NYC	Read Replies (2) \| Respond to of 1573558

Paul, Now, AMD has to come up with >500 MHz SRAM chips for the off-CPU L2 cache. They may go with half speed L2 to manage cost. With 128K L1, you will have a fewer cache misses. Joe

To: Paul Engel who wrote (39174)	10/13/1998 3:04:00 PM
From: Steve Porter	Read Replies (1) \| Respond to of 1573558

Paul, Well that was the other thing I wasn't really happy with. Just what speed will the L2 cache run at. Will it be 500Mhz, 250Mhz, 333Mhz, or what? More questions have been raised by the announcement than have been answered. Steve

To: Paul Engel who wrote (39174)	10/13/1998 3:20:00 PM
From: Ali Chen	Read Replies (1) \| Respond to of 1573558

Narrow thinking, Pal: <AMD has to come up with >500 MHz SRAM> AMD has come up with "a programmable high-performance backside L2 cache interface", as you might notice from the press release. The K7 can accommodate whatever will be available from AMD SRAM partners. As you may guess, the size of L2 is not an issue - a SlotA designer can put any size he want/can - 1M, 2M, 4M, 8M... You may exercise yourself to continue the series... For a 1:1 L2 SRAM, Intel has already demonstrated that for a processor with 12-14-stage pipeline, some extra L2 latency/bandwidth does not matter in terms of real-world performance - compare again your lovely Xeons (1:1 L2) with regular P-II (2:1 L2). For the latter, a cacheline burst is probably 4-2-2-2, which is still smaller than the P-II 12-clock deep execution pipe, and many OOOO (Other Out-Of-Order) instructions can mask the processor bubble anyway. Sorry if it is slightly off your chemical background. Now go woodchopping, your $5000 router has cooled down already...