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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (39180)	10/13/1998 2:39:00 PM
From: Paul Engel	Read Replies (2) \| Respond to of 1573682

Joe - Re: ". With 128K L1, you will have a fewer cache misses." But when you get a cache miss, the K7 is going to suffer speed penalties compared to the Xeon or upcoming Coppermine and Cascades chips. Paul

To: Joe NYC who wrote (39180)	10/13/1998 3:01:00 PM
From: Tenchusatsu	Read Replies (4) \| Respond to of 1573682

Joe, re: <They may go with half speed L2 to manage cost. With 128K L1, you will have a fewer cache misses.> If the K7 debuts at 600 MHz, a half-speed L2 cache will be going at 300 MHz. This is pretty underwhelming when the front-side bus is running at 200 MHz. It can be done, especially since an off-chip L2 cache will still have lower latencies than RDRAM or SDRAM. But since the L1 cache is 128K and the front-side bus is 200 MHz, the off-chip L2 cache would need to be huge, like at least 1 MB, in order to make a noticeable difference in performance. The K7 could also start with a full-speed L2 cache, but then the cost would knock K7 out of the mainstream and into the more expensive (but higher-margin) server/workstation market. I guess all this is the reason why AMD is keeping the L2 cache details vague. Like Intel and the P6, AMD may want to push the K7 to different market segments by tweaking its off-chip L2 cache. Tenchusatsu