SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Steve Porter who wrote (39204)10/13/1998 3:57:00 PM
From: Ed Sammons  Read Replies (1) | Respond to of 1573849
 
RE: I just hope he stole the FPU ;-)

My hope is that when AMD licensed the EV6 protocol, they also licensed other parts of the Alpha technology, especially the FPU.



To: Steve Porter who wrote (39204)10/13/1998 4:10:00 PM
From: Joe NYC  Read Replies (1) | Respond to of 1573849
 
All,

What's the difference between memory controller (on chip - M3) and L2 cache controller (on chip - K7)?

Joe



To: Steve Porter who wrote (39204)10/13/1998 4:18:00 PM
From: Joe NYC  Respond to of 1573849
 
Steve,

Two General Purpose 64-bit Load/Store Ports into D-Cache
- 3-Cycle Load Latency
- Multi-banking Allows Concurrent Access by 2 Load/Stores


How does it compare to M3:
16K, 4-way, non-blocking data cache (3 cycle access, 1 load port, 1 store/fill port

Joe