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Technology Stocks : 3DFX -- Ignore unavailable to you. Want to Upgrade?

To: Patrick Grinsell who wrote (8518)	10/21/1998 7:19:00 AM
From: Patrick Grinsell	Respond to of 16960

Gary T. on single board SLI set-ups... On item 3: SLI in the case of 3DFX designs requires a PCI host bus. What I was referring to was the ability to SLI above the PCI bus, to alternate scan lines without having to provide an extra full card. If you define the device in such a way to allow SLI by having a chip upgrade. 3D Labs can do this with the Glint series on professional boards. I don't pretend to understand the technical issues behind these capabilities, but am writing this note to suggest what I would like to see in the future. I understand what you are saying - the problem is if it's on one card, you need the bridge chip. In a new design they just started talking about (ships summer of 1999) 3D labs uses an instance of one of their Gamma chips as an AGP bridge. Their system is around $5000, not exactly a consumer product. I doubt if you will see consumer-upgradable SLI system where you plug in another rendering chip. At the speeds these things are running, I don't believe it's very feasible. Plus the socket and extra chip cost, starts making things expensive. A better solution might just be a larger chip that renders twice as fast??? Remember once you go SLI, you have additional cost because some memory like texture memory is duplicated (so as to provide enough texture memory bandwidth to each rendering chip). Gary, What about the TNT solution to processing two pixels during each clock cycle (terminology correct?)? Isn't that effectively SLI? Can't wait for the next 3dfx next-gen card! Yes - it's comparable to a super-scalar CPU within 1 chip, as opposed toa multi-chip multi-processor. Until cpus run out of room on 1 chip, you will find cpu companies putting super-scalar execution units and even multiple processors inside 1 chip. When you run out of room on 1 chip, then you will see multiple chips, if necessary. Likewise for graphics - multiple pixels or textures per clock within 1 chip will probably be most common design over the next few years. There are a few good reasons for using multiple chips however - you get smaller die which sometimes makes the cost a lot less (big chips yield terrible), and you get more memory pins (and bandwidth). Pat's Notes: Looks like the nextgen board will be a multi-chip parallel processing unit. I don't see how they could otherwise fit everything into one chip. If they could have done that, they probably would have put on an extra TMU in Banshee. It won't be an "SLI" implementation per se, but it will have the parallel power. Pat