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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (41512)	11/15/1998 11:40:00 PM
From: Elmer	Read Replies (3) \| Respond to of 1574096

Re: "Perhaps you should elaborate on this. You have suggested that it will be impossible to test the K7 bus, yet the Intel/Rambus problem sounds far more serious. " An interesting situation isn't it! Let us consider the scope of this problem. First the K7. According to available information, AMD's next generation processor, the K7, will feature a BSB rather than including on board L2 cache. AMD was not clear whether the BSB would be full core speed or half speed. In addition, AMD indicated that at some future point the offboard cache would be brought back on board, in whole or in part. It would seem that putting the L2 cache off chip is not the best solution from a performance standpoint unless it would be accessible just as though it were on chip. That's where the problems start. On chip it would operate at full core speed and the bus could be 128 bits wide. Should AMD decide to do 128 bits externally it would be costly because of the added pincount and boardlevel trace count. If AMD goes 64 bit then it will effectively cut the bandwidth in half. Should AMD go full frequency they are faced with the problem of what to use as a production tester, because their current generation has only had to face the challenge of testing the 100mhz FSB of the K6x. If the K7 runs at 500mhz+ then full speed BSB is undoubtedly beyond the performance of their production equipment. In fact, half speed BSB is almost certainly also beyond the range as well. What to do, especially in view of the roadmap which has the L2 cache eventually pulled back on chip, thus reducing the test requirement to the 200mhz datarate FSB, which is possibly in the range of their existing equipment? Does AMD go out and dump many many $millions so they can buy testers to test the K7 BSB on an interm basis, just until AMD gets their act together enough to pull the L2 back onboard? Should AMD decide to go half speed BSB they are again cutting their bandwidth in half. The combination of half speed BSB and half width BSB would effectively cut the bandwidth to 1/4 and probably leave them standing out in the cold. So where do they get these $million+ testers and what do they do with this investment once they move the L2 back on die and 500mhz+ testing is no longer needed? Remember Intel has indicated they will include huge L2s on die. Intel will not need to make this investment for expensive testers because they will only have to test at the speed of the FSB. To me this is a clear indication that AMD has no confidence in their ability to do large SRAM arrays and may very well explain the problems they have been having to date. To answer the question of where do they get these ultra highspeed testers? The answer is, they don't, because the only ones available are not suited for a production environment and the cost would be prohibitive for the low volumes AMD would be shipping before they redesign the K7 to include L2, thus eliminating the need for this expensive equipment in the first place. AMD is faced with pissing away $millions just to get what amounts to K7 samples out. 2. Rambus. Intel faces an even more challenging problem trying to test a Rambus interface, and so do the DRDRAM memory suppliers. I do not know the exact solution they will choose but whatever it is, the cost will be spread across 100s of millions of devices with only 8 or 16 bits needed to be tested, as opposed to the very small volume and large L2 interface bus width AMD will need to test for the early versions of the K7 with offboard L2. Some interesting papers were presented on this topic at this years International Test Conference in Washinghton DC a couple of weeks ago. AMD did not present. EP