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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (41521)	11/16/1998 1:23:00 AM
From: Ed Sammons	Read Replies (1) \| Respond to of 1574194

Intel will not need to make this investment for expensive testers because they will only have to test at the speed of the FSB. Actually the Xeon's have full speed .5-2MB BSB at 450MHz. If I remember correctly, the K7 BSB can run at either full or half speed. Your seem to question AMD's ability to test K7's full speed BSB, however you do not question Intel's ability to test the full speed BSB of the Xeon. Why is that? You seem to be saying that AMD can not afford the required testers, but do not question Intel and the full speed BSB of the Xeon. Won't Intel be in the same situation when the L2 cache is placed on the silicon in .18um? Did Intel piss away beaucoup bucks for testers?

To: Elmer who wrote (41521)	11/16/1998 2:09:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1574194

Elmer, It would seem that putting the L2 cache off chip is not the best solution from a performance standpoint unless it would be accessible just as though it were on chip. This should have minimal performance impact for K7. Remember that K7 has a 128K L1 (4X the size of the current Xeon's and PII's.) A few clocks extra latency going off chip for L1 misses will not be devastating to performance. Obviously it would be better to have the L2 onboard, but the large L1 will nullify most of the impact. If AMD goes 64 bit then it will effectively cut the bandwidth in half. Bandwidth from the L2 is not very important for performance of single processor systems. Data is only moved one cache line at a time, never in large blocks which would make the bandwidth a significant factor. Scumbria

To: Elmer who wrote (41521)	11/16/1998 11:15:00 AM
From: Ali Chen	Read Replies (2) \| Respond to of 1574194

Elmer <That's where the problems start. On chip it would operate at full core speed and the bus could be 128 bits wide.> <..half speed BSB and half width BSB..> That's where the problems start, Elmer, in your head. Why not to assume from the very beginning that the cache "could be XXX bits wide", where you took a liberty to assume 128. Why 128 only, not 256? or 512? You also can assume that the cache may want to run at double the core clock, why not? More "bandwidth is better, is not it? Then your "logical" threat could be much greater. AMD should "cut bandwidth" even more than your great numbers - 8 times, or 16 times, or even 32 times! What a horror! Sell AMD immediately, they cut your made-up bandwidths at horrible rate! In short, you just demonstrated that you know very little about the overall business. You sound like a test technician attending local Community classes on PC literacy for self-education. Some other nonsense in your post were already caught by Ed and Scumbria. Get rest, Elmer. You seem to operate under assumption that AMD is a company of dorks. I don't think it is a truly constructive assumption for your investment strategies.

To: Elmer who wrote (41521)	3/29/2001 9:30:54 AM
From: Scumbria	Respond to of 1574194

Elmer, Intel faces an even more challenging problem trying to test a Rambus interface, and so do the DRDRAM memory suppliers. I do not know the exact solution they will choose but whatever it is, the cost will be spread across 100s of millions of devices with only 8 or 16 bits needed to be tested, as opposed to the very small volume and large L2 interface bus width AMD will need to test for the early versions of the K7 with offboard L2. Sounds like RDRAM systems will be a lot cheaper than K7 systems. Scumbria