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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (41570)	11/16/1998 5:58:00 PM
From: Maxwell	Read Replies (2) \| Respond to of 1572507

Scrumbria: <<All modern microprocessors are starved for data running real world apps. Until dram latencies dramatically improve, the value of one architecture vs. another is limited to the entertainment of CPU architects.>> The current standard is 100MHz SDRAM. It is cheap and plenty. Given that criteria how can you make your system run faster. K7 answers that by A) Larger L1 cache (128K vs 64K in K6-2) B) Bigger buffer C) Better decoders (3 general vs 2 complex and 1 simple in PII) D) More execution units E) 200MHz bus vs 100MHz F) Backside L2 cache up to 8M (same as PII) G) L3 cache H) Bigger buffer (for 72 instructions in flight) The idea is to utilize the current technology and build a fast and cheap system. That is what the K7 did. Maxwell

To: Scumbria who wrote (41570)	11/17/1998 11:46:00 PM
From: Steve Porter	Read Replies (4) \| Respond to of 1572507

Scumbria, Unless anyone really cares about synthetic benchmarks which fit in the L1. I care about those and I'll tell you why: I can write code that fits inside a normal (64K) L1 cache and data that fits in there too.. therefore, with the advent of instructions in 3d-now and soon KNI, I can preload the data into the cache, run compute intensive operations (matrix mults, etc.) at very high-speed. What the high DRAM latency really forces is for programmers to re-learn how to code. A lot of programmers today have no idea about tight code. I believe that anyone who is learning to code in school today should be forced at some point to spend an entire semister programming on a Commodore 64.. then they will learn about clock-counts and the like. Regards, Steve