SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (30318)11/19/1998 10:38:00 PM
From: Craig Freeman  Read Replies (2) | Respond to of 33344
 
Scumbria, if latency is the problem, at ~$25 per MB of 100MHz L2 cache, it would seem far more cost-effective to add L2 than to buy faster processors. Yet 1MB of L2 cache is about the all you see on Socket 7 mobos. Why?

Craig



To: Scumbria who wrote (30318)11/20/1998 12:18:00 PM
From: Steve Porter  Read Replies (2) | Respond to of 33344
 
Scumbria,

A dram page miss will cost 100 clocks on a 1GHz CPU. All the fancy CPU architecture in the world will do nothing to resolve this issue.


Not true and you know it Scumbria!... there are lots of things you can do to hide this latency. The most important would be for the CPU to be able to prefetch data into the caches. The first CPU that can do this automatically will have a tremendous advantage.

Steve


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News