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To: Steve Porter who wrote (30326)	11/20/1998 12:38:00 PM
From: Joe NYC	Read Replies (1) \| Respond to of 33344

Steve there are lots of things you can* do to hide this latency.* I guess Scumbria assumed that no changes from current CPU designs are made, you are assuming changes can be made. If it was easy, I think it would have been done by now. The most important would be for the CPU to be able to prefetch data into the caches. I guess the tough part is to figure out what which data to prefetch, which to me is difficult, if not impossible. Joe

To: Steve Porter who wrote (30326)	11/20/1998 12:55:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 33344

Steve, Not true and you know it Scumbria!... there are lots of things you can do to hide this latency. The most important would be for the CPU to be able to prefetch data into the caches. The first CPU that can do this automatically will have a tremendous advantage. Power PC has cache touch instructions for preloading the cache. No one has figured out how to write a compiler to take advantage of this. The compiler has no way of accurately predicting which cache accesses will miss, and you certainly don't want unnecessary dram accesses tying up the CPU. Scumbria