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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Jim McMannis who wrote (43143)	12/10/1998 1:25:00 PM
From: Kevin K. Spurway	Read Replies (2) \| Respond to of 1571929

Re: bigger L1 One thing nobody has really realized is that a 500 MHz Katmai is going to outperform a 500 MHz Xeon clock for clock. Hope Intel has plans to quickly port the Katmai core into the Xeon infrastructure. Kevin

To: Jim McMannis who wrote (43143)	12/10/1998 1:42:00 PM
From: Ali Chen	Respond to of 1571929

<This ploy is just like the one they used on the Pentium MMX.. > No Jim, I think this time it is different. For Pentiums there was a heavy dependence on L2 cache performance that blocked DRAM accesses. Every L1 miss was a big miss. Therefore the increased rate of L1 hits due to bigger L1 size on MMX directly resulted in fewer L2/DRAM activity, and contributed to the bottom line of Pentium-"MMX" "32k-L1" performance. For the PPro DIB architecture the size of L1 (and even L2, as we see from Celery-A example) does not matter too much on most business applications. Therefore the effect of new bigger Katmai in Winstones is obvious: it will be close to ZERO, as it was with all other P-II "improvements" (Elmer, au...h!). The Katmai may show some small improvements in number-crunching applications and benchmarks like SPEC. I suspect Intel knows this and that is why they market the Katmai for hi-end workstation sector only and not for consumer lines.