Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Pastimes : Dream Machine ( Build your own PC ) -- Ignore unavailable to you. Want to Upgrade?

To: Dave Hanson who wrote (4093)	12/10/1998 8:09:00 PM
From: AreWeThereYet	Read Replies (3) \| Respond to of 14778

Dave >> the ECC circuitry is built right in, needing only an extra standard parity bit to function. << I'll have a extreme hard time to imagine how's that work. I suspect the ECC circuitry is only the logic to detect when an error occur by decoding the ECC portion a byte. You still need ECC memory in order to benefit from self error correction memory r/w. ECC memory has at least 3 extra bits for every byte while even/odd parity require only 1 bit. I hope someone who know more about the BX chipset can confirm or disprove me. Thanks aC