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To: AreWeThereYet who wrote (4102)	12/10/1998 8:39:00 PM
From: Spots	Read Replies (2) \| Respond to of 14778

>>I'll have a extreme hard time to imagine how's that work Me too, Andy. Thanks for asking the question I was trying to formulate. Parity can detect it but magic would have to correct it without the extra bits. Or I'm nuts, but by my bit count I'm not nuts. Conceivably high entropy <g>. All distinct possibilities. BTW, you say 3 bits per byte, but ECC works on bigger hunks, doesn't it? More like 32 or 64 bits? My impression, anyhow. I must go count up some more bits. Lessee, here, add 1, modulo 7, carry the 3 ... <ggg>. Spots

To: AreWeThereYet who wrote (4102)	12/10/1998 8:48:00 PM
From: Sean W. Smith	Read Replies (1) \| Respond to of 14778

Andy, The ECC is block error correction. Don't think of it as a bit for every byte as with parity. Think of it as 8 Bits for 64 Bits. This block code can correct 1 bit error and detect 1-4 Bit errors. The bits don't have to be byte addressable as the code is computed for the entire double-word (64 bits). I can't guarantee thats how intel does it but the algorithm is common and we use in our products on 64 bit memory interfaces. Here some general info.... asti.dost.gov.ph I have a reference to the actual circuitry at work but not handy. Sean

To: AreWeThereYet who wrote (4102)	12/10/1998 10:42:00 PM
From: Dave Hanson	Read Replies (2) \| Respond to of 14778

aC, on ECC, "what Sean said" <g.> Seriously, his description is consistent with what I recall of the BX chipset--not that he wouldn't be more likely to know something like this than me anyway. :) Now in theory, of course, there could be multiple-bit errors that this ECC circuitry couldn't correct. But it's save to say that with the reliability of modern memory, the chances are truly infinitesmal. And I bet the chances of a parity error occouring that BX couldn't at least <>detect is all but mathematically impossible.