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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Jim McMannis who wrote (44234)	12/29/1998 12:28:00 PM
From: Scumbria	Respond to of 1572919

Jim, An explanation why the K6 loves cache. Seems that the CISC-RISC decoder needs to be fed all the time. The reason that large caches are necessary is very simple. When an instruction or data fetch misses the caches, it requires 30-100ns to retrieve it from dram. In contrast, an L1 hit requires less than 3ns, and an onboard L2 hit requires less than 10ns. Every time a cache miss occurs the processor stalls. Microprocessor architectural performance is mostly determined by cache size. Not surprisingly, the fastest x86 processor (K7) has the largest L1. Prior to K7, the fastest x86 processor per clock was MII which had the lowest effective latency L1 cache (64K unified.) Any argument about the need for cache is derived from this fundamental principle. Scumbria

To: Jim McMannis who wrote (44234)	12/29/1998 3:25:00 PM
From: Bill Jackson	Read Replies (2) \| Respond to of 1572919

Jim, Good article, explains why AMD does so well. I am sure intel chose as they did for a reason though? Can you intermix risc instructions in with x86 instructions and have those ones bypass decoding and go directly to the execution unit? Seems doable and is there a convergence in that direction to allow RISC to gradually supercede CISC by allowing both to run? I can also see how they can add even more parallel decoders and execution modules to get even more throughput, but how far can that go? At some point you must hit diminishing returns. Bill