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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (44595)	1/2/1999 3:16:00 PM
From: Kevin K. Spurway	Read Replies (2) \| Respond to of 1571385

Re: "will have L2 that runs at 1/3 the core rate." Use your head. Where is AMD going to get 300 MHz SRAMs cost effectively in five months? I'm guessing Intel will add a 1/3 multiplier to their L2 as well. Kevin

To: Elmer who wrote (44595)	1/2/1999 4:02:00 PM
From: Ali Chen	Read Replies (2) \| Respond to of 1571385

Elmer, <Intel's Xeons will have (which will have integrated L2 at up to 2 Mega Bytes or more).> Where did you get this delirious ideas about "integrated 2MB L2"? From what future? Are you a close buddy of Time Traveller? Intel can barely yield 1MB of STANDALONE SRAMs at 450MHz today, but you are ravving about 2MB integrated... After all, the 2MB of L2 is the yesterday of server processors. And again, stop your groundless drivel about bandwidth, sizes and pin count. People who design caches know their business much better than you. What does matter is the overall performance of the whole memory hierarchy, including L1,L2, TLBs, and the main memory response dynamics, with heavy accounting for typical data locality for applications on the targeted market. It is not only the L2, but the whole thing that must be carefully balanced. And cost of silicon is not the last parameter here. We appreciate your test and packaging expertise, but you are way off in your assessment of cache architectures.