SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Ali Chen who wrote (45653)1/12/1999 7:56:00 PM
From: Tenchusatsu  Respond to of 1573696
 
Thanks, Ali, for the civilized response. Being my elder, I'll give you the respect you deserve.

<Once again: the same control/address signal on Pentium-II bus cannot switch at every clock as the definition of a "full" clock rate would require; it can be changed at the second clock only, or TWO TIMES SLOWER than the clock rate. Therefore I coin it as 1/2 bus speed. As you see, nothing has been "twisted" here, just broader view on the subject. Therefore I endorse the "latched bus protocol" as a work around the problem, not a innovative engineering solution. Sorry.>

This doesn't matter since (1) the transactions are pipelined, and (2) one request can only be made every three clocks. So having a turn-around clock or two doesn't matter if the control signals for the next transaction isn't needed for three clocks.

Besides, the request phase of a transaction is two clocks long. There are no turn-around clocks between each clock of the request phase. This proves that even the request bus runs at full clock speed. Of course, because requests can only be made once every three clocks, there's a single turn-around clock between every request phase in a fully occupied bus.

<Within the context of your discussion this alludes to some inferiority of K7 as compared to "Full-speed" super-duper Pentium-II-III bus.>

This wasn't my intention. The K7 bus is most definitely not inferior to the P6 bus. In fact, I find it cleaner than the P6 bus just from looking at the "foils."

I thought I had read somewhere that the request port in the K7/EV6 bus runs at 100 MHz, while the data bus runs at 200 MHz. I assumed that this meant the bus is 100 MHz double-pumped. You're right, saying it was "double-pumped" was misleading. But to me, it still doesn't matter how fast the request port is in relation to the data bus as long as enough requests can be made to keep the data bus busy. If the request port really does run at 100 MHz, this means that requests will have to be made at least once every two clocks in order to keep up with the 200 MHz data bus. This isn't a big deal.

Tenchusatsu



To: Ali Chen who wrote (45653)1/12/1999 10:55:00 PM
From: Elmer  Read Replies (1) | Respond to of 1573696
 
Re: "I twist nothing. The old synchronous bus
technology just does not work at high frequencies
at full speed. That's why the FULL CLOCK setup time
is necessary to make it work.
Once again: the same control/address signal
on Pentium-II bus cannot switch at every
clock as the definition of a "full" clock
rate would require; it can be changed at the second
clock only, or TWO TIMES SLOWER than the clock
rate. Therefore I coin it as 1/2 bus speed. "

Ali, your nonsense isn't fooling anybody. What other transaction type are you proposing, asynchronous? Get a clue. The P6 bus requires about 3ns setup time and less than 1ns hold, not the "full clock" that you mistakenly claim through your confused fog. The bus architecture allows for easy scaling to higher frequencies, and will go FAR higher than the 133mhz suggested for the upcoming "Camino" chipset. The P6 bus certainly can switch on every clock that matters, when it's transferring data. The notion that it is a "half speed" bus is a "half witted" notion. You also fail to grasp the concept that the P6 bus architecture was designed for SMP. The reason there are at times delays between control signals is because the processor does not own the bus after issuing a transaction request. What seems like a dumb idea to your simple mind is the whole beauty of the split transaction bus. Multiple requests can be posted from multiple agents and they can be serviced out of order. None of this is possible if an agent camps on the bus. There is a reason for all this Ali and the SMP server world is far more in touch with it than you are. That's why Xeon based servers are taking the server market by storm and you are still babbling about full clock setups and half speed busses. Ask your technician friends to explain it to you. They obviously must have a better grasp than you do.

EP