To: Ali Chen who wrote (45653 ) 1/12/1999 7:56:00 PM From: Tenchusatsu Respond to of 1573696
Thanks, Ali, for the civilized response. Being my elder, I'll give you the respect you deserve. <Once again: the same control/address signal on Pentium-II bus cannot switch at every clock as the definition of a "full" clock rate would require; it can be changed at the second clock only, or TWO TIMES SLOWER than the clock rate. Therefore I coin it as 1/2 bus speed. As you see, nothing has been "twisted" here, just broader view on the subject. Therefore I endorse the "latched bus protocol" as a work around the problem, not a innovative engineering solution. Sorry.> This doesn't matter since (1) the transactions are pipelined, and (2) one request can only be made every three clocks. So having a turn-around clock or two doesn't matter if the control signals for the next transaction isn't needed for three clocks. Besides, the request phase of a transaction is two clocks long. There are no turn-around clocks between each clock of the request phase. This proves that even the request bus runs at full clock speed. Of course, because requests can only be made once every three clocks, there's a single turn-around clock between every request phase in a fully occupied bus. <Within the context of your discussion this alludes to some inferiority of K7 as compared to "Full-speed" super-duper Pentium-II-III bus.> This wasn't my intention. The K7 bus is most definitely not inferior to the P6 bus. In fact, I find it cleaner than the P6 bus just from looking at the "foils." I thought I had read somewhere that the request port in the K7/EV6 bus runs at 100 MHz, while the data bus runs at 200 MHz. I assumed that this meant the bus is 100 MHz double-pumped. You're right, saying it was "double-pumped" was misleading. But to me, it still doesn't matter how fast the request port is in relation to the data bus as long as enough requests can be made to keep the data bus busy. If the request port really does run at 100 MHz, this means that requests will have to be made at least once every two clocks in order to keep up with the 200 MHz data bus. This isn't a big deal. Tenchusatsu