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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (45660)	1/13/1999 1:46:00 AM
From: Ali Chen	Read Replies (3) \| Respond to of 1573729

Elmer, <The P6 bus requires about 3ns setup time and less than 1ns hold, not the "full clock" that you mistakenly claim through your confused fog.> Listen up, "bus expert". I did not invented the "Latched Bus Protocol" idea. I did not write the "Pentium Pro Family Developer Manual" Volume 1. I did not draw the protocol diagrams in Chapter3 nor in Chapter4. I cited phrases exactly from these sources for you and Tech. You can hype whatever you wish how your Xeons "take market by storm" or hurricane or whatever. It does not change the fact that none of the request/bus arbitration signals are sampled with one clock distance; there are always at least two clocks between the sampling points along the same signal, with rare exceptions. Period. I brought this poit just as an argument in polemic about K7 half-speed request protocol Tench was alluding to (non-intentionally, as he said, and wrongfully as I said). You, in turn, are confusing the logical protocol ("split transactions", SMP, "out of order" ) with physical requirements for a transaction to arbitrate for bus and proceed. Even Tench indirectly agree with me. The question whether all this affect performance is the different one. Yes, until the request phase is shorter than data phase (4 data clocks at least), this limitation of ONE request per THREE clocks (see Tench post) does not matter and is not a bottleneck, so who cares how far in advance those signals must be asserted. However it may change in case of double-pumped data: the slow control bus may become a bottleneck. I repeat for you, Elmer: the Intel's manual explicitly states that those signals must be asserted the whole clock before they are get sampled. Not 3ns before and 1 ns after. Again: in order to be there 3 ns before the sampling moment, the control signals are required (by Intel) to be set the whole clock in advance. This is required to offset various bus propagation and reflections. Full clock in advance. This is called "Latched Bus Protocol", by Intel. Comprehende? By Intel. I have nothing to do with this, I just spotted a general observation. <The bus architecture allows for easy scaling to higher frequencies, and will go FAR higher than the 133mhz suggested for the upcoming "Camino" chipset.> Certainly, if you have the whole clock for the signal set-up, no wonder it can be done in 7 ns, just as the current PCI-33 requirements! <The P6 bus certainly can switch on every clock that matters, when it's transferring data.> No kidding, in data phase. But not in the arbitration/request phase. According to all documents (and reality) that "other bus stuff" goes effectively at a HALF-RATE. It is amazing how you have no shame trying to squirm from this apparent (for now) fact! Have you ever seen the Intel manual I am referring to, Elmer? I bet you have no idea why the Intel bus is limited to 4 processors only! <Ask your technician friends to explain it to you.> It does not seem you are doing a good job, dear test technician. I can understand your frustration, Elmer: it must really hurt when you see your ideals crushed and half-baked. I am really tired to teach you basics. You fail again.