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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Ali Chen who wrote (45669)1/13/1999 2:20:00 AM
From: Elmer  Read Replies (1) | Respond to of 1573746
 
Re: "Elmer, <The P6 bus requires about 3ns setup time and less than 1ns hold, not the "full clock" that you mistakenly claim through your confused fog.> Listen up, "bus expert". I did not invented the Latched Bus Protocol" idea. I did not write the "Pentium Pro Family Developer Manual" Volume 1. I did not draw the protocol diagrams in Chapter3 nor in Chapter4."

No, obviously you didn't write it and it's questionable if you really read it but there's no doubt you don't comprehend it. Your confusion is apparent for all to see. You are a perfect example of how someone can be shown something and yet not see. Your inability to grasp the principles is so deeply embedded that neither I nor others on this thread can dislodge your misconceptions. There comes a point where it no longer makes sense to show the blind, speak to the deaf, nor reason to Ali. On this matter I have reached this point. Good night Sir.

EP



To: Ali Chen who wrote (45669)1/13/1999 4:22:00 AM
From: Tenchusatsu  Read Replies (1) | Respond to of 1573746
 
Elmer: <The P6 bus certainly can switch on every clock that matters, when it's transferring data.>
Ali: <No kidding, in data phase. But not in the arbitration/request phase.>

Request phase too, Ali. The request phase is two clocks long. This means that the request information is switched on both clocks without a turnaround cycle in between.

Ali: <Yes, until the request phase is shorter than data phase (4 data clocks at least), this limitation of ONE request per THREE clocks (see Tench post) does not matter and is not a bottleneck, so who cares how far in advance those signals must be asserted. However it may change in case of double-pumped data: the slow control bus may become a bottleneck.>

Well, there's two ways to solve this problem. Either double the cacheline size, or reduce the number of clocks between requests to two.

Anyway, we've killed this topic many times over.

Tenchusatsu



To: Ali Chen who wrote (45669)1/13/1999 1:18:00 PM
From: Petz  Read Replies (1) | Respond to of 1573746
 
Ali, re:P6 bus, is the transaction rate important? Can't a single transaction fill an entire cache line? (just asking)

Petz