SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Kevin K. Spurway who wrote (45718)1/13/1999 2:54:00 PM
From: Bruce A. Thompson  Read Replies (1) | Respond to of 1571873
 
Volume, RSI, Momentum, Price. All up

$32 11/16 and climbing. FEELING GOOD!!

Bruce



To: Kevin K. Spurway who wrote (45718)1/13/1999 3:33:00 PM
From: Elmer  Respond to of 1571873
 
Re: "Seems a bit strange to me, considering that the K6-2 shares most of the same speedpaths and we know that it ramps pretty well. It could be that the article is a little unclear--guess we'll have to wait for this afternoons CC for the answers."

I think AMD is suffering from some noise coupling effects from the L2. We know they can do a K6 core and we know they can do SRAM, but can they do both?

EP



To: Kevin K. Spurway who wrote (45718)1/13/1999 4:33:00 PM
From: Scumbria  Read Replies (2) | Respond to of 1571873
 
Kevin,

Here is my most likely scenario:

At the time the K6-3 concept was conceived, their speed goal was probably about 350 MHz. They probably architected the L2 latency for 350 MHz. Subsequently, Intel raised the MHz bar and the cache couldn't keep up.

I have seen this scenario dozens of times in CPU designs, where a 2% architectural performance feature is added at a 15% clock speed cost. Most CPU architects tend to be very learning challenged when it comes to architectural performance vs. clock speed trade offs.

Scumbria