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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tony Viola who wrote (46238)	1/15/1999 5:52:00 PM
From: Scumbria	Read Replies (2) \| Respond to of 1570931

Tony, What I want to hear is that the long path was caused by the TLB half early address clock copies being late by 200 picoseconds, causing the L1 cache data out to be late by the same amount and the fix was a painful one of having to discrete all the L1 data out lines. Guess which speedpath that is? It is the address translation/cache lookup path. exchange2000.com That path has been fixed architecturally in K7 (with a three cycle cache lookup.) Watch out Intel. Scumbria