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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (46447)	1/18/1999 12:36:00 AM
From: Yousef	Read Replies (1) \| Respond to of 1583677

Elmer, Re: " ... what kind of speed path "mask problem" could be fixed in just the top metal layers, when it clearly didn't affect their ability to produce slower product? No one has presented a reasonable case, imho." Elmer, I will present just such a case ... BTW, I have seen this done before. Typically a speed path that prevents a part from working at a high speed (say 400mhz) works just fine at lower frequencies. This speed path usually is just slightly marginal at the high frequency. Thus, a slight change in either the drive currents (Idsat) or the RC (Resistance & Capacitance) can increase the margin to where the "speedpath" no longer limits the chip. I have seen designers take a "speedpath" routed in lower level metal and move that up to the thicker (lower Resistance) levels to provide more margin. BTW, this requires more than one mask to be changed (sometimes all the interconnect levels), but doesn't require any frontend changes. Re: " This seems like a real kludge to me as a real fix probably have included lower level mask plates as well." Can't argue with you there, Elmer ... This is not an "eloquent" way of designing ... More like "trial and error". Make It So, Yousef

To: Elmer who wrote (46447)	1/18/1999 12:53:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1583677

Elmer, What is being debated here is, what kind of speed path "mask problem" could be fixed in just the top metal layers, when it clearly didn't affect their ability to produce slower product? No one has presented a reasonable case, imho. Microprocessor designers always create "spare gates" (unused logic) which connect to top level metal layers, to allow for metal only logic changes. It is standard practice to fix speedpaths and bugs with available spare logic, many times involving only one metal layer. Scumbria

To: Elmer who wrote (46447)	1/18/1999 5:27:00 PM
From: Petz	Respond to of 1583677

RE: AMD speedpath problem - not wanting to search through the last 120 posts, has anyone considered that the problem may have been related to signal routing rather than an actual circuit design problem? For example a bus path may have been too close to another bus path, etc. I suspect it is noise-related rather than delay-related. This would explain 1)wide distribution of max frequencies (noise is unpredictable), 2)failure at high clock rates (more noise), 3)failure at higher bus clock rates (more noise), 4)rumored appearance of Vcc=2.3v devices (higher Vcc reduces noise problems). Regarding the last point, an AMD spokesman confirmed via email that the K6-3-400 will not use a 2.3 volt Vcc. See JC's webpage, chiptech.com 99/01/17, 5:55pm - Hey....remember that stuff put up; on the AMD webpage accidentally letting us know about the K6-2-450 and K6-3's voltage requirements? Very unhappy, I emailed Bob from AMD in the unlikely chance that it was somewhat incorrect about the 2.3v requirement (which would make it unworkable with a select few SS7 boards). Well, to my near-infinite surprise and happiness, I got confirmation that the K6-3-400 will in fact run at 2.2v officially. Petz