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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (46475)	1/18/1999 2:02:00 AM
From: Yousef	Read Replies (1) \| Respond to of 1573379

Scumbria, Re: "Here is a quiz for you: ..." Scumbria, you still haven't answered my question to you about your "spare gate" hypothesis. How do you effectively route to these spare gates and improve the "speedpath". This IS the problem with your proposed solution ... THINK MAN !!! Do you just "randomly scatter" spare gates across the chip ?? Make It So, Yousef

To: Scumbria who wrote (46475)	1/18/1999 11:03:00 AM
From: Elmer	Read Replies (1) \| Respond to of 1573379

Re: "You have a long path coming into a latch, with short paths coming out. The long path coming in affects the clock speed of the design. How would you fix it with spare gates? A. By adding an even number of inverters to the clock wire driving the latch. Q2. Why would you use an even number of inverters? ;^)) " Your spare gates are just delay elements and your even number preserves the clock phase for the latch. Clock tree distribution is probably the most critical layout and timing issue for highspeed devices so this is a real kludge. It would likely be very sensitive to process variation thus inviting unpredictable yields. Sound familiar? EP