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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (47706)	1/28/1999 6:24:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1580058

<Longer latency dram access.> Huh? The P6 bus has nothing to do with DRAM latency. As soon as the first clock of the request phase is seen, the chipset initiates the access to DRAM. I would imagine that for single processor systems, there is no arbitration phase because the single processor simply parks on the bus and keeps possession. The only way the Super 7 platform can achieve lower latencies is via the motherboard SRAM cache. No P6 bus motherboards have any SRAM cache, though I can't think of a reason why they can't have one besides the lack of necessity. Tenchusatsu

To: Scumbria who wrote (47706)	1/28/1999 6:40:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1580058

Re: "The P6 bus offered Intel: 1. Split transactions. Essential for MP. Little value in a single processor system. 2. AMD couldn't copy it. Intel was hoping that the motherboard manufacturers would phase out Socket 7, and take AMD out with it. Unfortunately for Intel, K6/MII market share got too large and spoiled their plans. 3. Potentially higher bus clock speeds. This was not needed because the backside L2 was on the CPU side of the bus." So you do acknowledge that the P6 bus has advantages. I assume then you retract your accusation that Intel did it to damage AMD. Clearly if the P6 was to be successful in SMP systems Socket7 had to go. The enormous success Intel has achieved with the PPro and now Xeon SMP systems proves the decision to drop Socket7 was the right decision. The fact that Intel didn't provide a Socket7 version, thus ensuring AMDs continued success seems to be what's bothering you. EP