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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Dave B who wrote (14973)	2/2/1999 3:07:00 PM
From: jopawa	Read Replies (2) \| Respond to of 93625

Just now hitting the wires "officially". 14:50 [RMBS] RAMBUS UPPED TO OUTPERFORM FROM NEUTRAL - MORGAN STANLEY. John

To: Dave B who wrote (14973)	2/2/1999 3:20:00 PM
From: Bernard Super	Read Replies (1) \| Respond to of 93625

To summarize: 1. Boxmakers will roll out RDRAM-capable boxes in June. So Rambus starts a ramp-up in royalties from RDRAMs and RACS in the third quarter - hence a possible positive earnings surprise in the Oct 14 earnings report. 2. The HP deal involves a lot of RACs that carry a substantially higher royalty % (and still high, IMO, despite the fact that HP undoubtedly negotiated a relatively favorable deal). 3. Since the IPO, IMO, the stock price has been driven by supply and demand, and is otherwise completely arbitrary. Between now, and when the mainstream institutions get in (IMO after some 3 quarters of accelerating earnings), the stock price will rise only to the degree that new waves of the more speculative funds and individual investors pile on, and compete for the relatively small float. Comments? Bernard (long and long term)

To: Dave B who wrote (14973)	2/2/1999 3:29:00 PM
From: Bernard Super	Respond to of 93625

From The Register: Posted 02/02/99 1:02pm by Mike Magee IBM, HP, Intel and AMD leak new technology Major chip manufacturers are set to unveil new microprocessors at a conference in the US in mid-February. The agenda of the IEEE Solid State conference, lists presentations from executives from IBM, AMD, Intel and HP, and accidentally discloses details of chips they have in the offing. According to the programme HP will show a 64b PA RISC chip using a .25 micron process, together with 1Mb of level one cache data and 0.5Mb level on instruction caches. The processor will run at 500MHz on a 21.3 x 22mm square die. IBM Micro will be showing a G5 chip for the S/390 platform, using a .15 micron chip running at 600MHz and running at 500MHz in a 10+2 shared environment. AMD will show its K7 at .25 microns and describes its out of order FPU, which it claims will execute FPU instructions at two FLOPS per cycle, 3DNow! SIMD instructions at four FLOPS per cycle peak rate and up to three MMX SIMD instructions per cycle. Intel is demonstrating a 600MHz IA-32 chip, according to the agenda. ®

To: Dave B who wrote (14973)	2/2/1999 6:30:00 PM
From: Glenn Norman	Read Replies (2) \| Respond to of 93625

Yo_Dave &Ms. Betty P.,,.............Ihave not finished catching up on all the post yet so excuse this if someone else has already noted it. The "DELAY" (if there turns out to be one) is not based on 600 MHz speed it is that Intel is having problems scaling the chipset to utilize RDRAM in 2, 4, and 8 way processor configurations. The "HYPE" on the speed is a non-issue. There will be some intense meetings going on at the FEB. Intel Conference concerning high end multi processor scalability with RAMBUS BUS configurations. If you will go back and look at the stock holders meeting figures on usage you will see that SERVERS are a very low usage of RDRAM in both 99 and 2000 and that they show to be scheduled to still be using SDRAM100 on the PC100/PC133 bus, this is the REAL issue with the new chipsets for RDRAM NOT THE 600 MHz speed! Salude to all the "BUSSERS" -- Norman!