SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Cirruslvr who wrote (48158)2/2/1999 9:38:00 PM
From: Elmer  Read Replies (1) | Respond to of 1571808
 
Re: "AMD will show its K7 at .25 microns and describes its out of order FPU, which it claims will execute FPU instructions at two FLOPS
per cycle, 3DNow! SIMD instructions at four FLOPS per cycle peak rate and up to three MMX SIMD instructions per cycle"

Incredible!! TWO FLOPS per cycle for FPU and FOUR FLOPS for MMX SIMD.

That kind of tells you how accurate "The Register" is.

EP



To: Cirruslvr who wrote (48158)2/2/1999 10:40:00 PM
From: Paul Engel  Respond to of 1571808
 
Cringe - Re: "How many FLOPS per cycle can the K6-X and PII/III do at peak rate?"

AMD generally does two earnings FLOPS per year.

Three FLOPS in a good year.

Paul


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News