IDF: Much work lays ahead for Rambus systems, Intel says
By David Lammers
EE Times
(02/24/99, 2:20 p.m. EDT)
PALM SPRINGS, Calif. — Intel Corp. has pushed back the official launch date for Rambus-based desktop systems to September, or about three months later than originally planned. But company executives at the Intel Developer Forum steadfastly denied that Intel would cave in and support an interim PC133 memory architecture.
Confirming reports that had been swirling for weeks, Pat Gelsinger, an Intel vice president and general manager of the company's desktop operation, said Intel was "not ready for volume production" of full-speed 800-MHz Rambus systems incorporating a 133-MHz system bus. Gelsinger put a portion of blame on memory module makers.
Gelsinger said Intel has no intention of backing off from its goal of introducing full-spec Rambus systems with a 133-MHz system bus, and will do so "late in the third quarter."
"Memory transitions are hard, and we don't want to do little ones," Gelsinger said in a rebuff to an interim PC133 memory specification.
During his keynote address, Gelsinger demonstrated what he called a "tour de force" prototype system that included a Pentium III processor, Direct Rambus DRAMs operating at the full 800-MHz specification, a 4X-speed AGP port, the Camino chip set supporting a 133-MHz frontside bus, and the instruction-level support for streaming data in 3-D graphics.
Michael Slater, principal analyst with Micro Design Resources (Sebastopol, Calif.), said the delay won't hurt Intel much. The 0.18-micron version of the Pentium III processor, code-named Coppermine, will be ready in the third quarter, at frequencies in the 600-MHz range — fast enough for consumers to take notice. Combined with the Rambus memories and a faster frontside bus, the Coppermine/Camino/Rambus combination will be successful, despite the three-month delay, Slater said.
Peter MacWilliams, an Intel Fellow at the Intel Architecture Labs (Hillsboro, Ore.) took a long-term view of the delay. It's "no big deal when you look at it from the perspective of where we are going over the next few years," he said.
But MacWilliams listed a number of challenges, from minor tweaks to major headaches, that need to be dealt with over the next six months. The overriding issue is "the interaction of all of the different pieces," what he called "the thousands of ingrediants" to the system recipe. The September launch includes three months for system OEMs to work out their own design issues, following three months to resolve some critical issues still facing the Rambus infrastructure.
For instance, the printed-circuit board and module industry overall has yet to come to grips with the 28-ohm impedance (controlled to ±10 percent) specification, which is a much tighter tolerance than the module industry faced in the PC100 era. A greater percentage of the modules will be made by the large DRAM vendors themselves, but many smaller vendors are not compliant. MacWilliams said the Rambus technology "is pushing the industry right to the edge [of its capabilities]. The need to make well-formed transmission lines with a minimum of stubs, all of this is very different than the tolerance in the PC100 generation."
In addition, Intel has received clock chips from four vendors, but the silicon from only one of the four was "compliant to the spec," MacWilliams said. Other vendors will join the market soon. "The Rambus technology is basically very solid," he said. "For the clocks we will be going back to tighten up the jitter window, which is 50 picoseconds. For the clocks, the vendors just need to tweak their PLLs a little tighter."
More importantly, five of the market's eight RDRAM vendors have supplied Rambus-in-line memory modules (RIMMs) to Intel, but "none were fully spec compliant," MacWilliams said. Design tweaking is part of the "normal cleanup" for any new memory architecture, he said.
Also, Intel's own Camino chip set has a number of "errata" which need to be stamped out. Further steppings are needed to boost the yields on the parts to support full-spec Rambus memories operating at 800 MHz.
Another concern involves die-size penalties for the Rambus DRAMs. Compared with SDRAMs, Rambus DRAM die are from less than 10 percent to more than 30 percent larger, with an average of about 20 percent. MacWilliams declined to speculate about cost premiums.
Further anxieties are raised by the worsening financial situation of Japan-based electronics giants, and by the merger of Hyundai and LG Semicon. DRAM prices have firmed of late, and Intel expects companies will invest in Rambus capacity. And while the DRAM industry's three dominant suppliers — Hyundai, Micron and Samsung — may have well-funded programs, the flood of bad news from still-important DRAM suppliers such as Hitachi and NEC may impact how quickly they will ramp to high volumes.
Once Intel turns on its own 0.18-micron manufacturing machine, DRAM vendors must achieve an equally steep ramp. Most DRAM makers now have the 128/144-Mbit RDRAM density as their main target, and the pushback to September will make the 128/144-Mbit strategy even more attractive. Producing the second generation of those parts on a 0.18-micron process will require investments in more advanced lithography tools and other front-end equipment, which will make production a much more expensive proposition than the back-end test and assembly equipment that has received so much attention to date.
Fallback strategies
At a standing room only session on the memory transition, Intel executives explained that Intel has no problem with companies that plan to use SDRAMs at the 133- and 166-MHz speed grades for graphics subsystems. But the speakers were adamant that Intel has no plans to support a PC133 specification, even though independent chip set vendors may do so.
In the early going of Intel's Pentium III generation, many system OEMs will use Intel's BX chip set with PC100 SDRAMs, and wait until a supply of 800-MHz RDRAMs develops.
For OEMs that want to use the Camino chip set and the Rambus-optimized motherboards, 600-MHz RDRAMs could be used. MacWilliams conceded that for latency-intensive applications, the 600-MHz Rambus systems might not provide much of a performance boost compared with today's PC100-based systems. However, for 3-D graphics, where bandwidth is more important, he said the 600-MHz systems would provide a noticeable performance difference.
There are two other fallback options in Intel's road map, said Brian Johnson, a member of MacWilliams' staff at the architecture labs. One is the long-planned S-RIMM. An interface ASIC would reside on a RIMM and would translate the Rambus signal levels of 1.0-to-1.8 V to the 3.3-V CMOS signals used in the PC100 SDRAMs. That would allow OEMs to use Rambus-type motherboards and RIMMs while using SDRAMs as the memory-on-board. Then the S-RIMMs could be swapped for the genuine RIMMs when the RDRAM supply picked up.
Another option — first described at IDF — involves a "DIMM riser" that would plug into one of the three RIMM sockets on a motherboard. Two DIMMs, populated with PC100 SDRAMs, would be inserted horizontally into the vertical DIMM riser. Johnson said some mechanical issues, and resistance to shock and vibration, still need to be worked out, but the electrical soundness of the DIMM riser approach has been established.
The specifications for the S-RIMM and DIMM riser modules, and prototype RIMM Gerber files, will be posted on the Web.
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