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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Patsy Collins who wrote (74444)	2/25/1999 2:30:00 AM
From: Monica Detwiler	Read Replies (1) \| Respond to of 186894

Looks like Intel will have a Merced chip set ready to test the Merced whenever it is born - the first such chip set - the 460GX - has apparently been sent out for manufacturing. From the description of the packaging issues, this is going to be one hot potato. One interesting statement regarding Merced revenue : In 2001, Intel's microprocessor revenue will be split equally between 32- and 64-bit chips, he added. - if Intel's revenues of 32 bit chips remains constant at 1998 levels - let's say 20 billion dollars -the implication is that 2001 processor revenues could easily be 40 billion dollars (20 $B + 20 $B.) That sounds like serious money - a 25% compound annual growth rate - in three years. Intel discloses more details about the 64-bit Merced By Mark Hachman, Electronic Buyers' News Feb 24, 1999 (1:25 PM) URL: ebnews.com Palm Springs, Calif.At its Developers' Forum today, Intel Corp. disclosed more details about Merced, its forthcoming 64-bit microprocessor. According to Intel executives, Merced remains on track to sample by the middle of this year, and is scheduled to reach volume production by 2000. "We will ship more Merceds in the first year of production than all the other [64-bit] RISC guys combined," but excluding 32-bit RISC processors such as the PowerPC included in Apple Computer's Macintosh, said Ron Curry, director of marketing at Intel's Microprocessor Products Group in Santa Clara, Calif. In 2001, Intel's microprocessor revenue will be split equally between 32- and 64-bit chips, he added. Curry declined to address questions concerning the Merced's price, which is expected to be quite high, but did say that the chip is in the final stages of verification. According to Curry, the Merced will add another high-performance segment to Intel's product lineup, and not displace its established customer base for 32-bit microprocessors. "The [total available market] only needs to grow 15%..., or only a few hundred thousand four-way systems, for us to outsell the RISC guys," he said. At least one Merced-specific chipset, the 460GX, has taped out, said Gadi Singer, vice president and general manager of Intel's IA-64 processor division. The four-way 460GX will be joined by at least seven other chipset designs from OEMs. Intel has planned the Merced infrastructure to tape out on a staggered schedule, allowing the processor to be tested against as many components as possible afterward, he said. According to Curry, Singer was brought in to "jump-start" the Merced program about six months ago, when the chip's production schedule slipped. As previously disclosed by Intel, the Merced will feature three layers of cache; the discrete Level 3 cache has been designed and will be manufactured entirely by Intel. Merced's cache SRAM will actually integrate tag RAM and arbitration logic, which is a kind of logic that conventional PC cache SRAM typically lacks, Curry said. Intel demonstrated at the Developers' Forum "thermal models" of the Merced module, which appeared roughly similar to the size of the Pentium II cartridge. The dummy module produces the same thermal output as a functioning Merced chip, allowing customers to begin evaluating their options in cooling it. Instead of the typical combination of thermal spreader, heat sink, and cooling fan, Intel might use a heat pipe, a sealed tube that conducts heat away from the processor via a copper wire or water. Additional power-managment features will be included, Singer said, possibly including powering down portions of the chip that are not in use. The module, which uses Intel's organic land grid array (OLGA) packaging, will be designed to incorporate four separate cache chips. At least two cache configurations will be designed to address the high-performance and "cost-conscious" enterprise computing segment; one version will use 4 Mbytes of L3 cache. Neither Curry nor Singer would disclose the size of the level 0, 1, or 2 cache. A full-speed bus will connect the cache and microprocessor. Monica