SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Jim McMannis who wrote (50949)2/25/1999 12:16:00 PM
From: Scumbria  Read Replies (4) | Respond to of 1571864
 
Jim,

Could the cache be causing a problem, a heat problem?

I have to admit, I find this baffling. An L2 cache (if designed for low power consumption), should not be clocked except during an L1 miss. This only occurs on about 3% of cache accesses, so basically the L2 should be turned off 97% of the time. There shouldn't be any heat problem.

From the outside it appears that the K6-3 architects may have made a fundamental mistake and attempted to be too aggressive in the L2 design.

Scumbria



To: Jim McMannis who wrote (50949)2/25/1999 12:23:00 PM
From: Gary Ng  Read Replies (1) | Respond to of 1571864
 
Jim, Re: but as this CPUID balloons and the possibility of a Pentium II recall looms larger, the K6-III may be the right chip at the right time

Want to take a bet on this ? I am more incline to the side
that AMD is going to see red in Q1 and Q2.

Gary


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News