Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (50951)	2/25/1999 12:36:00 PM
From: Elmer	Respond to of 1572089

Re: "From the outside it appears that the K6-3 architects may have made a fundamental mistake and attempted to be too aggressive in the L2 design. " Gee now there's a new one. A product is a marrige between a design and a process and AMD has continually over designed what their process was capable of. That's the whole problem with AMD, in a nutshell. EP

To: Scumbria who wrote (50951)	2/25/1999 12:47:00 PM
From: kash johal	Read Replies (1) \| Respond to of 1572089

Scumbria, Re: L2 cache / heat problem Well I think that we can rule heat out: HEAT: It cannot be heat related. The Cache does not take that much power. And if it was causing them a problem they would have to LOWER the VCC and only be able to ship 400's. I think it must be Yield related. Clearly as they raise VCC they get a whole bunch more parts to pass the speed bin tests. My assumption on only the 400/450's was that they were going to ship the balance of speed bin failures as cheap laptop chips. We know that at 2.2V the CXT core yields around 50% of parts at 400Mhz and above at the most. Raising the VCC by 10% can easily raise that substantially (maybe as high as 70-80%). Basically it is a gaussian distribution and it is a pretty narrow spread with these newer processess. Yousef and Paul are absolutely correct that too high a VCC can damage the gate oxides and cause reliability problems. All semi companys are paranoid about such problems-so they guardband this quite agressively. I suspect that they came out with 2.2 to ensure absolutely no reliability problems with the 0.25 micron parts. Then as they have life-tested higher voltage parts thru high temp tests they may well have concluded that another 10% was no problem. In which case they can start using the more aggressive VCC. I am sure you know that Paul/Yousef are are doing some scare mongering on this issue. If AMD is shipping it they will have life tested with still quite some margin on the reliability issue. Regards, Kash

To: Scumbria who wrote (50951)	2/25/1999 12:50:00 PM
From: Jim McMannis	Read Replies (3) \| Respond to of 1572089

Scumbria, Could AMD have to jack up the voltage because of a heat problem? or jack up the voltage to get the cache to run right and that would result in a heat problem? If the later, would there be a quick design fix? Also, could getting the L3 to run right with the L2 cause any heat problem? I know I'm swimming here. Jim

To: Scumbria who wrote (50951)	2/26/1999 1:45:00 AM
From: Petz	Read Replies (1) \| Respond to of 1572089

Scumbria, re: An L2 cache (if designed for low power consumption), should not be clocked except during an L1 miss. This only occurs on about 3% of cache accesses, so basically the L2 should be turned off 97% of the time. There shouldn't be any heat problem. This is true, but AMD as a matter of policy finds the "program which generates the most heat" and requires that the K6-3 be stable at its rated frequency and 0.1volt below its rated voltage. There is probably some pathological program code out there that exercises the L2 cache and the FPU on almost every cycle. An FFT on a very large data set should do it. Petz