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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (51762)	3/6/1999 2:48:00 PM
From: Yousef	Read Replies (1) \| Respond to of 1572673

Ali, Re: " ... R-S-flip-flop may be built using two 2-NAND gates. If it has a 1T delay when flipping from 0 to 1 on direct output ..." And Ali, what affects the magnitude of your "delay" (T) ?? ... Is it the "process thing" ?? Your "intellectual weakness" in E-M shouldn't stop you from getting the right answer here !! <ggg> Make It So, Yousef

To: Ali Chen who wrote (51762)	3/6/1999 6:20:00 PM
From: kash johal	Read Replies (3) \| Respond to of 1572673

Ali, Re <Sorry Ali but you got things backwards. 'Sequential gates'? You mean combinational gates between sequential elements.> Just to jump in here. You were correct except for the terminology. There are always a "series" of logic gates ( Combinatorial function) required to perform a certain function. Designers split up this series by inserting a "clocked" element (a flip-flop - also known as a "sequential" element. The critical path is the slowest path thru the combinatorial gates including routing delay. So, by utilizing "pipelining" and adding additional sequential elements you have fewer combinatorial cells in the path and hence can run a faster clock. You lose some latency but you gain tremendously in overall clock speed and throughput. The PII family has more pipelining than the K6/K6-2/k6-3 family and gives a higher clock rate. The K7 is even more pipelined than the PII family and should give an even faster clcok rate than the PII in the same process. In summary Useless who keeps saying that Intel has a faster process by reference to the clock speeds achieved is spreading his usual FUD. There are reports that the K7 will be demonstrated in a few weeks at 600Mhz on AMD's 0.25 process at CEBIT and without any special cooling no less. So clearly you need a great architecture and a great process. Regards, Kash