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To: andy kelly who wrote (76329)	3/15/1999 2:00:00 AM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

andy - Re: " do you expect that the cost per system will go down vs. a comparable current Xeon chip? I don't know how the increased cost of a larger chip balances out with the savings that will result from not having to put the special high speed SRAM in the cartridge." This is an excellent question - which addresses trade-offs in silicon die costs as you integrate functions from two separate die (SRAM + CPU) into one monolithic silicon device. Basically, as you do this integration, the CPU size increases significantly and the cost/die goes up dramatically - even when yields are still good -- simply because the size of the integrated CPU/L2 cache is much larger than the CPU alone. For Cascades/Coppermine, this will be greatly offset by the simultaneous conversion to a 0.18 micron process. Now, the Pentium III on a 0.25 micron process is about 123 sq. mm. The DIXON chip - a Pentium II with integrated CPU + 256K L2 SRAM cache, on a 0.25 micron process - is about 181 sq. mm. Assuming that a 0.18 micron Coppermine - a Pentium III with 256K L2 cache - is similar to a "shrunken" DIXON, I would estimate that a 35% die area savings results (conservatively less than the 49% "theoretical" savings). Thus, Coppermine should be about (1-0.35)181 = 118 sq. mm on a 0.18 micron process, and will be the functional equivalent of a Pentium III with a FULL SPEED L2 cache with reduced latencies. The net result, for this case, is an approximate constant die cost (actually, it will be slightly higher due to more process steps and, accordingly, a higher wafer cost for the 0.18 micron wafers). But, the separate 512K L2 cache is ELIMINATED - for a net-net REAL reduction in silicon costs (note that the L2 cache for the Coppermine is only 1/2 the size of the Pentium III - but TWICE the speed). Now, assembly costs will be greatly reduced - only one die is assembled instead of 2 or 3. Moreover, TESTING costs are greatly reduced*. Only one die needs to be tested - instead of BOTH CPU and SRAM die - but TESTING and TESTER REQUIREMENTS are reduced ! No longer is an SRAM test at 275 (Pentium III) or 550 MHz (Pentium III XEON) required - which places extreme costs due to expensive testers capable of those speeds. The "separate" CPU must also be tested at those speeds to insure that the L2 cache interface runs at those speeds for Pentium III or Pentium III XEON chips. The Coppermine and Cascades chips DO NOT REQUIRE such strenuous tester capability. All the high speed cache access signals are generated on board the Coppermine/Cascades CPU and the complete CPU can be tested at 100 or 133 MHz (plus appropriate guard band), and the pin-count of the tester and interface boards are greatly reduced since the L2 cache data, address and control lines are eliminated - they are "invisible" since they exist internally on the Coppermine/Cascades chip. Hence, testing costs are GREATLY REDUCED. Couple this with reduced assembly costs, and the net "system costs" go down significantly. Further, a Coppermine chip can now be placed into a PPGA package, eliminating the Slot 1 paraphernalia. Thus, look for Intel's margins to rise - or hold steady if the prices are reduced - once Coppermine is introduced into high volume manufacturing. Cascades will also show reduced costs, but the Slot 2 packaging should remain. Note - some versions of Coppermine and Cascades will have integrated L2 cache LARGER than 256 K, and could go as high as 1,024K or even 2,048 K. Cost benefit analysis of these will "vary" accordingly ! Paul

To: andy kelly who wrote (76329)	3/21/1999 10:26:00 AM
From: andy kelly	Read Replies (2) \| Respond to of 186894

Good Morning thread: Interesting article in my local paper this AM. Headline says "Just say 'no' to Pentium III". It has a big picture of Jami Dover, Intel VP, holding up a PIII cartridge. I'm sure she will think twice about another photo op. with Cox News Service, originator of the story. Text of the story has this sentence, "Intel has said it expects to offer PIII chips by the end of the year with speeds as fast as 1 gigahertz...". Point of the story is why buy now when you can get a similar machine at a much lower price by year-end when the 1 GHZ chips come out! Author of article was Bill Husted. I wonder where he got the idea 1 gigahertz will be out by end of year. Andy