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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (52684)	3/16/1999 1:42:00 PM
From: Scumbria	Read Replies (2) \| Respond to of 1577019

A proposed experiment: I would like to see 3D benchmarks for several different systems with a constant cost of about $2000. 1. K6-3 with a professional graphics card. 2. Celeron with a professional graphics card. 3. Xeon/PIII with whatever graphics card fits in the $2000 budget. My guess is that the K6-3 and Celeron systems will blow away the Xeon system. This is a critical benchmark test for evaluating the worth of Intel's market segmentation strategy. I encourage everyone to contact the benchmarkers, and request they perform this experiment. Scumbria

To: kash johal who wrote (52684)	3/16/1999 2:36:00 PM
From: d[-_-]b	Respond to of 1577019

Kash, re: The key will be if and when they ramp dresden and start yielding high volumes in Q3/Q4. That "key" is broken, as that fab won't go into production until 1st qtr 2000.

To: kash johal who wrote (52684)	3/16/1999 4:14:00 PM
From: Shane Geary	Read Replies (1) \| Respond to of 1577019

re: "The key to the K7 is the 0.18 micron process. I doubt if AMD can yield any reasonable volumes with the die size at 180mm2." Not necessarily. There appear to be 3 problems with AMD yield. (i) Yield loss due to speed binning. A major problem with AMD at the moment is that they cannot yield high-speed parts. In process terms, this is primarily a question of siting the average channel length low enough to achieve high speeds (while avoiding yield loss due to sub-threshold leakage), and then controlling the channel length (primarily through excellent control of the polysilicon gate lithography/etch step). (ii) Yield loss due to the tungsten local interconnect used on the SRAM cell. This was news to me, but not a surprise. W processing is always very dirty. The effect will be die-size dependant (actually, more dependant on the SRAM area if this is where the problem is), and I can't see why it would affect the availability of high-speed parts (iii) Design fault(s) Yield loss due to speed binning won't be much affected by die size (yes, I can come up with cases where it will affect it, but in general it won't). The primary yield loss related to die size is the random defects on the wafers - primarily due to particles (include here the local interconnect issue). Dresden is a brand new fab - very clean equipment etc. I wouldn't worry about random defectivity too much (I presume the local interconnect problem is fixed by now, and it should be). Sure the K7 yield will be worse because of it, but that's not the key issue IMHO. No, far more important is how they plan to ramp Dresden, and on which process. Are they transferring a process running in volume elsewhere? If so, is the part they are making (K7) also running in volume on this process. If the answers to the above questions is no, then AMD will be ramping a fab with an untested design on a new process - asking for trouble. When things go wrong (and many things will) you have no 'baseline' to fall back on. It's hard to tell if a yield problem is a fab or design problem (and the worst ones are an interaction between the two). So what process will the K7 be run on initially, and what is the process roadmap?