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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Shane Geary who wrote (54085)	4/3/1999 3:52:00 PM
From: RDM	Read Replies (3) \| Respond to of 1570840

<Perhaps the best answer is " Don't need Cu at 0.25um, need Cu at 0.15/0.153um, some benefit at 0.18um"?> Wouldn't the answer vary some with chip architecture? High speed wires are important in architectures that have lots of long wires. High speed gates are more important in designs that do not have lots of long wires and have lots of cascaded gate delays. I have read from Scrumbria's and others that the K7 architecture has relatively few gate delays (perhaps 12 to 14) per clock supporting a higher clock rate/per gate speed than historic x86 CPUS. If there are lots of long wires in the K7 transferring a high speed due the copper might be more important than in another architecture.

To: Shane Geary who wrote (54085)	4/3/1999 3:59:00 PM
From: Process Boy	Read Replies (1) \| Respond to of 1570840

Shane - Cu vs. AlCu Nice summary of the various aspects of the Cu or not to Cu debate. I feel I need to clarify my position somewhat. My beef with AMD going to Cu at this point is what I believe to be an extremely high amount of risk for AMD. I brought up cross-contamination as one possible, worst case scenario that could be devastating. Any number of other process control issues with an immature process could also be just as devastating. Intel is going to go to Cu at .13um. I'm on board with this, as the process will have at least two more years under it's belt before critical product and fab transitions. I'm not anti Cu. Dual damascene is physically / topographically an elegant solution, as Shane stated. Also, from what I understand, at .13 Cu provides a big improvement in RC delay with regard to the total circuit, at least from Intel's perspective. One could assume that Intel put a lot of emphasis on reducing gate delay for .18, while putting enough emphasis on RC delay improvement utilizing AlCu and SiOF dielectric (mature processes). At .18um, Intel strongly believes Cu is not worth the risk when AlCu is more than adequate, at this point in time. Intel will probably ramp Cu in more than one fab, which provides margin. According to sources on this board, AMD's backup to Dresden is 100k-200k/mo. units at MOT. This is a pretty skimpy margin, IMHO. Again, I'm back to my AMD will have to execute flawlessly mantra. Enough said. PB

To: Shane Geary who wrote (54085)	4/4/1999 10:28:00 AM
From: Steve Porter	Read Replies (1) \| Respond to of 1570840

Shane, You know it's funny.. I'm not really a support of any MPU maker at the moment but I just had to jump into this wonderful cooper discussion that's raging.. It's funny to see that almost 1 and a half years after Yousef and myself got into this discussion (on the Cyrix thread I think it was), that people are comming to agree with our conclusion that Cu is pretty much only a neat news story until you get into the low teens, (.13-.11 micron), in terms of process size. Normally I don't agree with Yousef on many things, but it's funny to see how this one has stood the test of time.. Regards, Steve