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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (54354)	4/5/1999 9:24:00 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 1583656

<Not by much. The L1 accesses are pipelined. If the branch prediction was perfect there would be no penalty for the longer raw latency. AMD has estimated that the total architectural penalty for the extra lookup cycle is less than 5%.> Compared to what? A 64K L1 cache? An extra layer of cache? Scumbria, it's clear that masking the latency of the oversized L1 cache with pipelining isn't going to make that latency a non-issue. You also have to consider how data hazards are going to exacerbate the longer latency, and you know that the multiple execution units of the K7 are going to have a ton of data hazards to resolve. Rather, I think the oversized L1 cache is the result of a trade-off. It would have made more sense to go to an extra layer of cache (like Merced's L0/L1 cache), but this would be too complicated given the K7 development timeline. Thus, it's possible that the oversized L1 cache, for all the die area it consumes, will not impact performance all that much. But then again, you said yourself that the K7 design looked like the product of a grad student's research project. I guess it all boils down to marketing. No one is going to care about the added latency, or even its effect on performance, as long as AMD can advertize those MHz numbers. (Off topic, you'll probably say the same thing about Rambus DRAM. At least Rambus introduces no additional latency compared to PC100 SDRAM. Ask me again if you doubt me.) Tenchusatsu