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To: Scumbria who wrote (78165)4/9/1999 1:38:00 AM
From: Paul Engel  Read Replies (2) | Respond to of 186894
 
SCUM bria - Re: "VLIW is easier to design, and requires less logic in the critical path- but it carries the burden that the software must schedule it's own delays."

You are missing half of the IA64 picture.

The IA64 EPIC architecture provides some excellent features for overcoming memory latencies with predication and speculative execution.

The HALF that you are missing is the Software COMPILER program that is generating specific IA64 compilers to directly address, among other topics, data dependencies.

The compiler will spot dependencies, allowing a LOAD from a register prior to a preceding, possibly conflicting data store operation to the same register.

The IA64 architecture will then detect any subsequent fault, if it occurs, and re-issue the instructions to be executed with the "proper" data in the registers.

The "BIG PICTURE" is that the Merced/IA64 is not just a chunk of silicon but an Integrated System of Software Compilers and EPIC hardware that work TOGETHER to optimize throughput of the system.

You need to get a better understanding of the "SYSTEM" involved - you are clearly underestimating the magnitude of this project.

Paul



To: Scumbria who wrote (78165)4/9/1999 11:03:00 AM
From: Tony Viola  Read Replies (1) | Respond to of 186894
 
Scumbria, IA64 is not a classical (if there is such a thing) VLIW processor. Aren't you going way out on a limb with FUD here based on the wrong assumption?

Tony