SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Scumbria who wrote (55154)4/11/1999 5:14:00 PM
From: Process Boy  Read Replies (2) | Respond to of 1572649
 
Scumbria - Yes, new designs when implemented often need on Si speed path debugging.

This is one excuse for AMD's predicament, not a solution. Given the inherent scenario you have just described, and the fact that is is a given AMD is playing catch-up, how is AMD going to get out of their current predicament?

BTW, sometimes designs DO work right out of the box. Although I can't be more specific, several iterations of what I have described previously as "the most successful CPU's of all time" were shippable on the A0 stepping. Just FYI.

PB



To: Scumbria who wrote (55154)4/11/1999 6:22:00 PM
From: Process Boy  Respond to of 1572649
 
Scumbria & Thread: Register reports Transmeta in some doo-doo

193.122.103.82

PB



To: Scumbria who wrote (55154)4/11/1999 9:19:00 PM
From: Mani1  Read Replies (2) | Respond to of 1572649
 
Scumbria Re <<The shmoo looks good, and you send new masks off to the fab. Three weeks later new parts come along and show a different problem which was not present in the samples you FIB'ed.>>

So who's fault is it? Such screw ups cause tons of damage, damage to the balance book and damage to share holder's value.

If you are saying that no one should be blamed since AMD has to be this aggressive and take chances to the point that makes this kind of screw ups expected and warranted, I disagree!

Mani



To: Scumbria who wrote (55154)4/12/1999 12:59:00 AM
From: Yousef  Read Replies (1) | Respond to of 1572649
 
Scumbria,

Re: "You do a FIB on a speedpath. You test the FIB'ed parts and run a
MHz vs voltage shmoo. The shmoo looks good, and you send new masks off to
the fab."

Is this a "design methodology" that you recommend, Scumbria ... This sounds
like a "happening" to me. If this is how AMD designs CPU's, then management
should be held accountable for this "craps" methodology. As I have always
said ... "AMD Happens" !! <ggg>

Make It So,
Yousef