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To: Scumbria who wrote (78472)4/11/1999 10:38:00 PM
From: Paul Engel  Read Replies (1) | Respond to of 186894
 
SCUM bria - Re: "The K7 L1 is pipelined and the MHz benefit will far exceed the architectural penalty. "

You have already stated that the L1 cache access takes THREE or more clock cycles I believe.

No matter how the cache is implemented, 3 clock cycles is 3 clock cycles.

Paul