Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (55730)	4/16/1999 5:44:00 PM
From: RDM	Read Replies (1) \| Respond to of 1578966

<from a Stanford undergrad EE class> EE-380 is a graduate class taken by PhD and Master's students.

To: Tenchusatsu who wrote (55730)	4/16/1999 6:36:00 PM
From: Process Boy	Read Replies (2) \| Respond to of 1578966

Ten - < The miss ratios, in general, are very small because it seems that the benchmarks are very small programs themselves and thus can easily fit itself and most of the data it works on in the L1 and L2 caches> How reliable of a gauge would these simulated values be? do they take into account redundancy features of the respective caches? Just curious. PB Jim, I don't think those scores that you posted can be valid scores. It's really hard for me to believe that super-confidential performance data from AMD and Intel would appear in a EE 300-level class. Anyway, for the moment, let's assume that the benchmarks are genuine. IPC stands for "Instructions Per Clock". The higher the IPC, the more performance you'll get at the same clock speed. L1 and L2 Miss Ratio is a measure of how well the caches do their job. Larger caches mean lower miss ratios, which mean fewer memory accesses have to go out to a slower memory subsystem. From your post, it seems that the IPC for the K7 and for Coppermine vary widely according to benchmark: IPC for: uncompress expresso fft Alt. Bench. K7: 1.413 1.104 1.143 1.257 CuMine: 2.066 1.758 1.133 0.806 This shows that for equivalent clock speeds, Coppermine has better performance on two benchmarks, equivalent performance on one, and lower performance on the "Alternative Benchmark." The L1 and L2 miss ratios, however, is no surprise. Coppermine consistently shows slightly higher miss ratios in both the L1 and L2 caches. This is because the L1 cache on CuMine (32K or 64K?) is smaller than the oversized 128K L1 cache of K7, and the 256K L2 cache on CuMine is also bound to be smaller than the minimum L2 cache size (512K) for K7. The miss ratios, in general, are very small because it seems that the benchmarks are very small programs themselves and thus can easily fit itself and most of the data it works on in the L1 and L2 caches. So if this document is the real thing, that means Coppermine will beat the K7 in some benchmarks, and fall behind in others. Of course, the veracity of this document depends on whether you trust inside information to come from a Stanford undergrad EE class. ;-) Tenchusatsu