Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (56054)	4/22/1999 4:14:00 PM
From: Scumbria	Read Replies (2) \| Respond to of 1570913

Ten, Take a K6-2, add an on-die cache, and that's a ramp? The K6-2 and K6-2 CXT cores were both introduced within the last year. AMD has had a remarkable ramp, and K7 will add to their bragging rights. Scumbria

To: Tenchusatsu who wrote (56054)	4/22/1999 4:39:00 PM
From: Jim McMannis	Read Replies (1) \| Respond to of 1570913

RE:"Funny how AMD is slower on this ramp than Intel is on the Pentium III ramp. Funny how AMD is also slower on this ramp than Intel was on the Mendocino Celeron ramp.".... Ten, I'm totally shocked at your reply. Usually tou are a straightshooter. Adding some instructions is the same as adding in die cache? I don't think so. As far as the Mendocino ramp. Remember that The mendocino started at 300 and 333. While the Pentium II was at 450. Intel had the luxury of ramping the Celeron much slower. AMD had to start the K6-III at 400 and 450. Jim