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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (57114)	5/3/1999 7:22:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1572598

<The small P6 cache helps the situation, but still implies that clock speed is limited by L1 cache access. Who knows how fast P6 would run with an additional pipeline stage for L1 access?> I don't know. I'm sure there are a lot of other factors limiting clock speed besides L1 cache. It wouldn't seem too hard to add an additional pipeline stage for L1 access. Pentium MMX added a pipeline stage to the original P5 core. (I don't know if that was because of the increased L1 cache from 16K to 32K.) Maybe Intel decided that for the Pentium III, a larger cache wasn't worth the effort, but SSE was. You make it sound like the longer latency L1 cache is the best invention since sliced bread, and perhaps with justification. But if it's that easy and that useful, why wasn't this trick used in Pentium III? Tenchusatsu

To: Scumbria who wrote (57114)	5/4/1999 12:12:00 AM
From: Process Boy	Read Replies (1) \| Respond to of 1572598

Scumbria - <Adding additional clocks for L1 access fixes both of these problems. I expect that K7 MHz will cause Intel a lot of problems.> By Jove YOU'RE RIGHT!!! I SEE IT NOW! The additional L1 clocks on K7's cache, WILL BE THE UNDOING OF INTEL!!!! I'd better escalate this info up the chain ASAP! <BG> PB