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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (57246)	5/5/1999 1:13:00 AM
From: grok	Read Replies (1) \| Respond to of 1572729

Re: <If the taken branch address is predicted properly by the branch target cache, the correct instructions will be prefetched into the prefetch buffer from a conventional cache. The BTC should be accurate more than 80% of the time.> It is not a question of prefetching. Think about issuing 6 instructions in one cycle. If the 3rd instruction is a branch then you're not going to process the last 3 instructions during that cycle. Three issue slots were wasted. Branch prediction just means that you don't waste 6 issue slots in the next cycle but it can't get you back the 3 that you just lost. <The performance advantage provided by a trace cache in an x86 CPU will be minimal.> Yes, I expect that it will be small too. But remember how much the market rewards minimal extra performance at the highend. I think that you have been posting that 10% gets you 500% higher price. Or something like that. <As for IA64, the ability to increase IPC will be dependent on intermingled multithreaded software which may or may not be practical to write. The best compiler people at IBM have been trying to figure out how to do this for decades.> If this "intermingled multithreaded software" does happen it won't be very effective without trace caches because wide issue needs trace caches. And with that I'm going to bed!