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To: cecil who wrote (2045)	5/10/1999 7:06:00 PM
From: schlep	Read Replies (1) \| Respond to of 2389

CAMS- expect delay through the actual 32x32 cam of <4.0ns (treat as Tsu of output register if pipelined). Routing on chip to get data to CAM is quite fast and could support your 140mhz if sources are place on same side of chip (its a big target so should be easy). Cascaded outputs would drive through a mux using encoded versions of the match output of each cam. 5x5 anti-aliasing, maybe altera.com can help you out. -schlep

To: cecil who wrote (2045)	5/18/1999 2:43:00 PM
From: Lewis M. Carroll	Read Replies (1) \| Respond to of 2389

You EE types seen SignalTap? Looks pretty neat but I missed a couple of things... 1. How much room should you reserve for the instantiation of the SignalTap block? 2. Do you have to use JTAG or can you packetize the data to ship out over an alternate method (ethernet frames maybe?) 3. Assuming you start your design including the SignalTap megafunction, how much re-compilation (if any) is necessary if you change the signals you want to watch? 4. Does the megafunction slow the rest of the 20K device it's in down at all? 5. Does Xilinx have anything like this in the works? L