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To: Steve Porter who wrote (32353)	5/17/1999 11:32:00 AM
From: kash johal	Read Replies (1) \| Respond to of 33344

Steve, Re: "Then it is being done wrong.. honest.." Steve millions of dollars are spent and being spent on just modelling the transistors. We have spent weeks here modelling a PLL block. WHich from a circuit complexity and size standpoint is small, but the noise,jitter etc specs are extremely tough to model accurately. And the likelihood is we will need a second turn to meet our specs (if we are lucky!!!). I suspect you live in a relatively linear board level world. The silicon side of the business has moved from simple digital design to a much more complex one. As an example the routing delays are now >>50% of the delay om most long routing paths. We are speeding them up by inserting inverters and breaking up the paths to meet timing delays. Anyhow if you could solve these problems you would be looking at saving the industry literally BILLIONS of dollars as products would come out faster cheaper etc etc. You may want to start your odyssey into solving these problems by learning about spice and BSIM models. If you make it let me know!!! Regards, Kash Johal