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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Alan Bell who wrote (29460)	9/13/1999 10:23:00 PM
From: kash johal	Respond to of 93625

Alan, Re:"The classic "conditions for short transmission line" are Length << (1/6) * (Trise/sqrt(LC) For a signal with a rise time of 2ns, the maximum acceptable length would be 2.3 inches." Alan I deal with CMOS ASICs all day. And rise/fall times are always well under 2ns. And i have never heard any of my customers using termination. For example AMD athlons use a 200Mhz point to point bus from CPU to chipset - I don't believe it is terminated at all. So I am at a loss to answer your question. Perhaps somebody designing MB's etc can help us. regards, Kash

To: Alan Bell who wrote (29460)	9/13/1999 10:25:00 PM
From: Dan3	Read Replies (4) \| Respond to of 93625

Time for someone from Intel or Rambus to step up with some final numbers, before Intel goes back to $45, and Rambus goes to $10. If this is a hoax or a fabrication, someone from Intel should say so. ========================================================== gotapex.com ---- snip I can't take a picture of it. My rep at Intel said that's a no-no. However, the good news is I am allowed to say all about how it performs and what it includes. ------- snip What I have is one of Intel's two i820 chipset motherboards, the VC820. The i820 is meant to replace the aging BX chipset as Intel's flagship desktop product. Here are a few items for us to drool over: 133/100mhz FSB speeds Asynchronous AGP and PCI/IDE speeds (no more worry with overclocking your peripherials, at least according to sources at Intel. YET UNCONFIRMED, as this motherboard cannot overclock) Accelerated Hub Architecture Support for the Coppermine CPU Native support for Rambus at 600 and 800mhz Native support for UltraDMA/66 PC99 compliant (no ISA slots. Woohoo!!) ----------- snip Anyhow, on to the test configuration. Motherboard: Preproduction Intel VC820 CPU: Preproduction Intel Pentium III 533B (3.6nS Latency 1 SRAM) Intel Pentium III 550 (3.6nS Latency 1 SRAM) Intel Pentium III 500 (4.0nS Latency 8 SRAM) Memory: 64MB 800Mhz Rambus RIMM Video: Diamond Viper 770 Ultra AGP4X TNT2 at 175mhz core, 200mhz memory, nVidia drivers v2.17 Hard Drive: Western Digital ATA/33 6.4G CD-ROM: Sony 40X OS: Windows 98 SE ------------ snip Conclusion Despite all of the apparent advantages the i820 had going for it, it was still beaten quite handily by the BX motherboard. The i820 has a supposingly more efficient Accelerated Hub Architecture, AGP 4X, a 133mhz Frontside Bus, and Rambus memory. The BX motherboard, on the otherhand, is still sailing on yesterday's technology. So how did this all come about? Well, it's difficult to draw any definite conclusions as of yet. There are still alot of unanswered questions. However, I will point out a few observations: The inf drivers. The drivers for the i820's system devices are probably not in their final form. I'm sure they will be improved in the days to come. I only tested the system with 64MB of ram. Even though the BX board was also tested with only 64MB, I noticed the i820 system was using the swapdisk MUCH more heavily. This caused very frequent pausing in Quake III, and was probably the leading cause in the skewing of the results. Perhaps with Rambus, you need more memory? I can not say for sure as of yet. All in all, we only ran a few tests. A wider range of applications may show differing results. Initial results starting to appear on the web do look grim for Rambus based systems, however. Look at some from Dell here. i820 chipset motherboards with Coppermine CPU's may show vastly different results then when mated with Katmai processors. Until then, we can only hope. So... don't throw out those old BX motherboards yet. Hopefully, Intel will be able to take care of these performance issues. If they do, you'll be sure to hear about it from us, if not then the defection rate to AMD is going to run rather high. ========================================================== Maybe they ARE being forced to use NAP mode after all, since the "wind tunnel" was rejected by the boxmakers, and this performance is the result. Dell could be in big trouble too. It didn't make much sense for VIA to tell Intel to buzz off unless the final numbers really are going to come in something like these. Dan

To: Alan Bell who wrote (29460)	9/13/1999 11:37:00 PM
From: grok	Read Replies (1) \| Respond to of 93625

Alan, did you work with Bill Gunning before he retired? Perhaps you could tell the thread what the G in GTL stands for.

To: Alan Bell who wrote (29460)	9/13/1999 11:45:00 PM
From: grok	Respond to of 93625

RE: <For a signal with a rise time of 2ns, the maximum acceptable length would be 2.3 inches.> Alan, do you know if DDR drivers are spec'd to have a controlled rise time of some particular value?

To: Alan Bell who wrote (29460)	9/14/1999 4:26:00 AM
From: John Walliker	Read Replies (1) \| Respond to of 93625

Alan, For a signal with a rise time of 2ns, the maximum acceptable length would be 2.3 inches. Thank you for expressing this so clearly. This is at the heart of the disagreement between Carl and myself. I suspect though that the rise times for SSTL2 are much shorter than this, especially when driving a short bus. I routinely find that perfectly ordinary HCMOS devices with typical rise times specified as a few ns often achieve rise times of as little as 400ps when loaded with only a few inches of pcb track and one CMOS load. I use a four channel, 2 Gsa/s simultaneously sampling HP digital oscilloscope with 800MHz FET probes to do measurements like this. (And I do know how to use it properly, especially with respect to artifacts relating to proper grounding. I usually do differential measurements to avoid them.) With lesser instruments the wild ringing that often occurs is simply not visible. John PS Yes, I did forget to compensate for the 10ns cycle time rather than 8ns as Carl pointed out. However, he was wrong to assume that power consumption scales linearly with frequency, because the sense amplifiers will draw a relatively constant current. Also, Samsung quote maximum currents for Rambus parts, whereas IBM appear to quote typical values for supply current of DDR devices. Therefore I think this error will have little or no effect on the final outcome of the calculations.

To: Alan Bell who wrote (29460)	9/15/1999 8:00:00 AM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi Alan Bell; Re: "For a signal with a rise time of 2ns, the maximum acceptable length would be 2.3 inches. So a system could be left unterminated if the data signals are less than 2.3 inches." I don't have the spec in front of me, but my guess is that the rise time would be somewhat less than 2ns, so rule of thumb length would be less. But instead of using a thumb rule, modern practice is to simulate. In the case of the hypothetical DDR system we have been talking about, most of the wires are data bus wires. So it is these we should consider first. Since it is a data bus, the primary concern is that setup and hold be met on the receiving flip flop. It is possible for a bus that rings pretty long to still meet setup and hold times. The address lines are running at a lower frequency, and are only sampled at one edge per 10ns. So while they have more pins, and thus worse ringing, they also have more time available for the ringing to die out. The effect of the ringing is to reduce the "data eye." But since we are using 8ns parts with a 10ns period, we already have a nanosecond of extra eye time on the data bus, and a full 2ns of time on the control bus. In addition, as you will find in the SSTL_2 specification, this logic family is specifically designed to be immune to a certain amount of ringing. My coworker who knows the most about these sorts of things says that it will work with no termination, but in reality, the engineer would have to run simulations if more than one RDRAM chip were placed on the data bus. (The hypothetical example we were discussing only had one bank of DDR.) On the other hand, there is no doubt that the clock lines need to be correctly terminated, though, and I felt guilty all day yesterday for not mentioning this in my post. What can I say? It was very late, and I have been very busy. I expected to be inundated with posts saying that I was an idiot, you guys are really too kind to me. You go on to say: "But if they are longer than this, termination is required." As noted above, this statement is necessarily true only for the clocks. In fact, common practice is to terminate all clocks regardless of the length. This is to avoid double clocking and uncontrolled skew. But the next sentence: "This will then use the kind of power that John describes", is not correct. This assumes that the only termination is the parallel type, which is not the case. Here are some quotes from and a link to an applicable Triquint (TQNT) application note (they make high speed clock driver chips): Terminating Clock Lines page 3 Series Termination Series termination, as shown in Figure 4, is the most common termination scheme used in clock distribution schemes. It consumes less power than other termination techniques and requires only a single resistor. The second example illustrates the use of series termination to minimize reflections. page 5. Advantages and Disadvantages of Series Termination Because series termination does not require additional power, it is a good choice when power dissipation is a critical design concern. When driving CMOS inputs, the steady-state power at the output is near zero, triquint.com Your choice of parallel termination for the DDR designs is a poor choice, and one that good memory designers are unlikely to make, though I would be inclined to include parallel termination on the one master clock, at least on the prototypes, and would probably include DNIs on the other control lines. By the way, if the data bus does give termination problems, (not in the design we are discussing, but in some larger design), these are traditionally alleviated with series resistors. In other words, my calculations for DDR power consumption are quite correct. Rambus is a power hog, there is no way around this fact. -- Carl