To: Proud_Infidel who wrote (32559 ) 9/22/1999 5:40:00 PM From: Proud_Infidel Read Replies (1) | Respond to of 70976
SIA technology roadmap might be stalling out By Jack Robertson Semiconductor Business News (09/15/99, 04:27:41 PM EDT) SAN JOSE -- Is Moore's Law running up against a "red brick wall" of unsolved critical processes in the Semiconductor Industry Association's International Technology Roadmap for Semiconductors? Maybe so. The upcoming 1999 revision of the roadmap is showing no progress in scores of technology barriers that are highlighted in red as having "no known solution," declared Juri Matisoo, vice president of technology for the trade group. "The discouraging point is that the 'red brick wall' of unsolved problems in the 1999 draft are the same as in the 1998 revision. We haven't made much progress at all," the SIA executive pointed out. This would certainly be a shocking turnaround in chip technology. In the past several updates of the roadmap, chip generations often were accelerated as technology advanced faster than originally was projected. The current draft of the 1999 roadmap revision, for example, moves up the 0.10-micron microprocessor generation by another year to 2001, Matisoo noted. SBN reported in July that the draft update continues a two-year interval from the 0.14-micron MPU generation in 1999, which also represented only a two-year span from the 0.20-micron generation. A separate roadmap schedule for DRAMs calls for the 0.13-micron generation to begin in 2002, the SIA vice president said, the same timing that was laid out in the last revision in 1998. This represents the three-year pace that DRAM producers had sought. They had claimed they didn't need to speed up the jump from the 0.18-micron processing technology that is just now in its very early stages of production at memory fabs. But unless the industry starts making some progress in solving some of the "red-highlighted" technology barriers, future roadmaps may not show the fast pace of technology change that it has become accustomed to, Matisoo warned. Lithography is a good example of where more progress is needed. No solutions are yet in hand for defect densities of less than 80-per-layer--even for 0.13-micron processing. Critical gate dimensions have become an unsolved problem for 0.10-micron generation chips. In fact, researchers haven't figured out the solutions for any of the major chip design parameters for 0.10-micron generation. This includes design productivity, ability to test, reusable design methods on a chip, and near-RF speeds of system-on-a-chip. The same goes for interconnect. No one knows how to extend the dielectric constant for a metal insulator layer, which now runs from 2.5 to 4.1 for the 0.18-micron generation. There are a host of unsolved issues for moving the dielectric constant ahead for upcoming 0.07-micron chip generation. They include barrier-cladding thickness, contact aspect ratio, via aspect ratio, and metal height/width aspect ratio. But Matisoo said the industry will get some breathing room to tackle these critical technical problems because the draft of the 1999 roadmap revision will switch back to three-year intervals between both MPU and DRAM generations after 2001. DRAM companies will continue on a three-year track, moving to 0.13-micron line sizes in 2002 and 0.10-micron in 2005. That will mean that DRAMs will fall four years behind the microprocessor generations, which the roadmap specifies 0.14-linewidths this year and 0.10-micron designs by 2001. SIA's Matisoo believed the debate over speeding up chip generations "has now settled down." Although the roadmap technical working groups continue to meet, he said they're now focusing more on the various technical parameters, rather than "the back and forth discussions on whether the timing of generations should be on two-or-three year intervals." The foreign working groups, which are inputting the roadmap for the first time, are going along with the updates made by the U.S. committees. These groups will continue to get inputs from counterpart panels in Japan, Europe, South Korea, and Taiwan. The foreign participants, he said, seem to be pleased with the consensus to retain three-year generation intervals after 2001. Except for lithography, the roadmap discussions are still pretty much a U.S. show. The final 1999 revision is slated to be released in Tokyo on Nov. 30 just before the opening of the Semicon Japan show.