To: Elmer who wrote (81240 ) 11/28/1999 2:14:00 PM From: Dan3 Read Replies (3) | Respond to of 1572580
Re: All this doesn't guarantee anything.... Hi Elmer, There is always the possibility that Willamettes will come flooding into the market in July, with large performance increases - or are they already halfway here? This late 1998 description of what would make the willamette/foster architecture outperform the coppermine suggests two differences: a deeper pipeline to allow better scaling, and a much improved cache =================================================== He noted that two new features of the Foster processor would be "a longer pipeline" and an "instruction trace cache." The longer pipeline allows Intel to achieve higher "clock" (megahertz) speeds, while the new type of cache eliminates performance bottlenecks in current chips. ========================================================news.cnet.com Now here is what was added to coppermine to help it compete with Athlon: ========================================================== The Pentium© III processor supports the high-performance Dual Independent Bus (DIB) architecture. The DIB architecture places the level 2 cache on a dedicated, high speed cache bus allowing for the system bus to be freed up from cache traffic. This provides significantly higher overall system bandwidth and allows for a dramatic improvement in system performance and scaleability. Non-Blocking Level 1 Cache The Pentium© III processor includes two separate 16 KB level 1 (L1) caches, one for instruction and one for data. The L1 cache provides fast access to the recently used data, increasing the overall performance of the system. 256 KB, Level 2 Advanced Transfer Cache (Available on certain versions as specified in Figure 1) The Advanced Transfer Cache (ATC) consists of microarchitectural improvements to provide a higher data bandwidth interface between the level 2 cache and the processor core that is completely scaleable with the processor core frequency. Features of the ATC include: Non-Blocking, full speed, on-die level 2 cache 8-way set associativity 256-bit data bus to the level 2 cache Reduced latency interface to cache data (as compared to discrete caches) =======================================================developer.intel.com If we've already seen a good part of the willamette/foster architectural improvements, then it may be a good year for AMD. When the other half of Intel's new architecture comes on line (additional, deeper pipelines and better queues), Athlon will be adding on die cache and memory bandwidth improvements (DDR266). And given that moving to .18 AL has required some time and effort, moving to .13 for foster will also require time and effort. With demand in Europe and Asia growing very quickly, and demand in North America continuing to be, at least, steady, both companies should have a good next year, and both companies should provide each other with competition. In such a scenario, I expect Intel to maintain a gradually rising market cap, and AMD to take off like a rocket. Intel with a market cap of $325B and AMD with a market cap of $65B by the end of next year? Regards, Dan