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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (90385)	1/29/2000 12:26:00 PM
From: steve harris	Read Replies (1) \| Respond to of 1572159

Dan, re:"processes" In over my head too...... It was discussed on SI last year, about how AMD would be delayed because of it's .18 copper process at Dresden. I'm sure Intel, with it's flawless foresight, will not have any problems with .13 and 300. steve eetimes is down, found one link about AMAT and tools, news.semiconductoronline.com{9C2CFF1E-8249-11D3-9A67-00A0C9C83AFB}&VNETCOOKIE=NO

To: Dan3 who wrote (90385)	1/29/2000 12:36:00 PM
From: steve harris	Read Replies (1) \| Respond to of 1572159

Dan, re:".13/copper" A little different spin on FAB 22 Doesn't appear Intel will try to swallow 300 and .13 at the same time. semiconductoronline.com{69E3E51B-D411-11D3-8C18-009027DE0829} Intel to Build First High Volume 300 mm Fab 1/26/00 Ending months of speculation, Intel Corporation announced it will build its first high-volume production manufacturing facility for 300 mm wafers in Chandler, AZ. The company said it will invest $2.0 billion to build and equip the facility, contingent upon local governmental approval. "Fab 22 will give us more manufacturing capacity in order to help us better address our customers' growing need for high performance microprocessors," said Mike Splinter, Intel senior vice president and general manager of the Technology and Manufacturing Group. The fab will begin production using Intel's 0.13-micron process technology with copper metallization on 200 mm wafers in 2001 and transition into the production of 300 mm wafers, Splinter said. The new fab will be located on the company's Ocotillo campus in Chandler, near Intel's existing Fab 12. It will have approximately 360,000 square feet, 133,000 of which will be cleanroom. Additional buildings adjacent to Fab 22 will include a four-story, 320,000 square foot manufacturing support building, a 123,000 square foot central utility building and several expansions to existing buildings and a warehouse. In addition, the company said it is continuing to evaluate other sites for additional manufacturing capacity, including its site in New Mexico.

To: Dan3 who wrote (90385)	1/29/2000 10:27:00 PM
From: steve harris	Read Replies (1) \| Respond to of 1572159

Dan, thanks to Mike Morley on the Intel thread, did some research on Sematech group. news.cnet.com. Discusses the item of polishing problems. "Under the Applied-Sematech alliance, the two organizations will essentially seek to develop a fungible standard for the polishing process for copper-based chips. While the polishing phase is but one stage in manufacturing, it presents one of the stiffer challenges for copper-based chips. Copper is polished faster than other elements contained in a semiconductor wafer. As a result, normal polishing procedures can erase copper circuitry."

To: Dan3 who wrote (90385)	2/23/2000 11:12:00 AM
From: Katherine Derbyshire	Read Replies (2) \| Respond to of 1572159

>>But the articles did mention that wafers that use copper were more sensitive to pressure variations during polishing steps and that a difficulty in processing the wafers was from pits developing during the polishing process as the copper wore away more quickly than other materials (such as aluminum) used previously. << Part of the problem is that metal polishing of any kind is a new process. Part of the problem is that aluminum forms a nifty passivating oxide during polishing, which helps to control the rate of material removal. Copper doesn't. Part of the problem is that copper polishing is very pattern-dependent--you might completely obliterate an isolated feature without reaching the desired thickness in dense features. And part of the problem is that copper is just a pain in the neck to polish. An alloy might be easier, but would also have higher resistance. Katherine