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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (98783)3/17/2000 3:24:00 AM
From: Goutam  Read Replies (1) | Respond to of 1571040
 
Scumbria,

The principle is quite simple. The deeper the pipe, the shorter the paths between latches. This translates directly into greater clock speed. It is a simple concept, but one which I have devoted most of my career educating management about.

I understand the deeper pipe lines allow the chip to clock faster because of reduced logic in each stage. Besides latency (effects of which can be offset from the gains with the resulting higher clock rates), are there any other reasons (die size,... ?) why it requires the management to be convinced in adopting deep pipelined designs? Also at what level (depth of the pipe line) the gains due to deep pipe line start leveling off?

Goutama



To: Scumbria who wrote (98783)3/17/2000 8:58:00 AM
From: Dan3  Read Replies (1) | Respond to of 1571040
 
Re: The deeper the pipe, the shorter the paths between latches...

Thanks for your post. It will be interesting to see Willamette performance on real applications. It will also be interesting to see how well all that double-speed pipeline logic scales.

Regards,

Dan


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